MRAM Bottom Electrode Layout With Separate Alignment Marks
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Solution Overview
Problem
The continuous shrinking of memory devices poses challenges in the patterning of magnetic tunneling junction (MTJ) layer stacks, leading to increased processing costs and surface damage due to additional lithography and cleaning processes, which affect the deposition quality of the MTJ layer stack.
Innovation Solution
A semiconductor circuit design with embedded MRAM cells, where the MRAM cell is integrated in the metallization layer, utilizing a bottom electrode and top electrode for signal conveyance, and alignment marks are formed separately to reduce the need for additional lithography and minimize surface damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If additional lithography and cleaning processes are performed for patterning MTJ layer stacks, then manufacturing precision is improved, but surface damage increases and deposition quality deteriorates
Solution Approach 1:
The patent separates the alignment mark formation from the MTJ layer stack patterning. Alignment marks are formed in dedicated mark regions using separate lithography processes, while the MTJ layer stacks are patterned in cell regions without requiring additional lithography steps. This segmentation allows each region to be optimized independently, preventing surface damage to the MTJ layers while maintaining patterning precision.
Solution Approach 2:
The alignment marks are formed in advance in the mark regions before the MTJ layer stack deposition and patterning processes. This preliminary action establishes reference points that guide subsequent patterning operations, eliminating the need for additional lithography and cleaning steps that would otherwise damage the MTJ layer surfaces.
2Measurement precision
If additional lithography and cleaning processes are performed, then alignment accuracy is improved, but processing costs increase
Solution Approach 1:
The substrate is divided into cell regions for MTJ layer stacks and mark regions for alignment marks. This segmentation allows alignment marks to be formed once in dedicated areas, providing accurate alignment references for all subsequent patterning operations without requiring repeated lithography and cleaning cycles, thereby reducing processing costs while maintaining high alignment accuracy.
Solution Approach 2:
The alignment marks formed in the mark regions serve as reusable reference patterns that are copied or referenced during the patterning of multiple MTJ layer stacks in the cell regions. This single formation of alignment marks supports the entire production process, eliminating the need for additional lithography steps for each MTJ pattern and reducing overall processing costs.
3Area of moving object
If continuous shrinking of memory devices is pursued, then device density is improved, but fabrication difficulty increases
Solution Approach 1:
The patent divides the substrate into distinct cell regions and mark regions, allowing the MTJ layer stacks to be scaled down in the cell regions to achieve higher device density without requiring proportional increases in lithography complexity. The alignment marks in separate mark regions provide robust reference points that simplify the fabrication process even as device dimensions shrink.
Solution Approach 2:
By pre-forming alignment marks in dedicated mark regions before MTJ layer deposition, the patent establishes a stable reference framework that remains valid even as MTJ feature sizes shrink. This preliminary action reduces fabrication complexity by eliminating the need for additional alignment lithography steps as devices are scaled to smaller dimensions.
Data Source
AI summary
A semiconductor structure and a method for forming a semiconductor structure are provided. A substrate having a cell region and a mark region is received. A dielectric layer is etched to expose a conductive line in the cell region and form a trench in the mark region. A conductive layer is formed over the cell region and in the trench. The conductive layer is etched to form a bottom electrode via in the cell region and a first mark layer in the trench.