MRAM Storage Cell with Angled Access Transistors for Dense Arrays
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge of improving the integration and performance of non-volatile magnetic random access memory (MRAM) while maintaining writing capability is urgent due to increasing storage density.
Innovation Solution
The storage cell design incorporates access transistors with long-side extension directions at a non-right angle (θ ≠ n·(π/2) to facilitate dense arrangement, enhancing integration and writing capability by connecting all four access transistors to a tunnel junction, and sharing word and source lines among adjacent cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If access transistors are arranged with long-side extension directions at right angles to bit lines, then the layout is simple and manufacturing is easy, but the storage cell size is large and integration is poor
Solution Approach 1:
The patent applies asymmetry by configuring the long-side extension directions of the active regions of the four access transistors to be substantially parallel to each other, forming a non-right angle θ with the bit line extension direction. This asymmetric arrangement allows transistors to be densely packed in one direction while maintaining electrical connectivity, thereby reducing the storage cell area and improving integration density.
Solution Approach 2:
The patent transitions from traditional orthogonal (two-dimensional grid) transistor arrangement to an inclined parallel arrangement that utilizes angular positioning. By changing the dimensional orientation from axis-aligned to angle-aligned configuration, the design achieves more efficient space utilization and reduces the overall footprint of the storage cell.
2Area of stationary object
If storage density is increased to improve integration, then the area per cell is reduced, but the writing driving capability deteriorates
Solution Approach 1:
The patent merges the source connections of all four access transistors to a common source node that directly connects to the tunnel junction. This merging of connection paths consolidates the writing current from all four transistors, amplifying the effective writing driving capability despite the reduced cell area, and ensures reliable data writing in high-density configurations.
Solution Approach 2:
The common source connection serves multiple functions simultaneously: it acts as the source for all four access transistors, provides the writing current path to the tunnel junction, and enables coordinated control of all transistors. This multi-functional design maintains strong writing capability while accommodating compact cell layouts.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces the size of the storage cell, improves integration in the storage array, and maintains strong writing capability, thereby enhancing the overall performance of the MRAM.
Implementation Method 1
A non-volatile magnetic random access memory (MRAM) is a random access memory which stores data according to resistive properties of memory. It uses different memory resistance values caused by different magnetization directions to record data.
Data Source
Figure 1~2
Figure 3~4
Figure 5
AI summary
Embodiments of the present invention provide a storage cell and a data read/write method and storage array thereof. The storage cell includes a bit line, a tunnel junction, and four access transistors. Each access transistor includes at least an active region. The active region includes a source. The sources of the access transistors are all electrically connected to a first end of the tunnel junction. A second end of the tunnel junction is electrically connected to the bit line, and the bit line extends along a first direction. The active regions of the access transistors are isolated from one another. Long-side extension directions of the active regions of the access transistors are the same, and a first angle θ is formed between the long-side extension directions of the active regions and the first direction; wherein θ is a non-right angle. The storage cell in the embodiments of the present invention is small-sized, so higher integration of a storage array can be provided when the storage cell is applied to the storage array.