MRAM Reference Cell Using Magnetically Annealed MTJ

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Conventional MRAM reference cell implementations require pre-programming of two cells to '0' and '1' states, leading to errors like stuck-at faults, shifting of reference values, and increased chip area, making them costly and inefficient.

Innovation Solution

Utilizing a single magnetically annealed MTJ cell in its native AP/'0' state to generate a reference voltage, with a programmable PMOS load to adjust the voltage to a midpoint between '0' and '1', and employing a mono pulse for reprogramming in case of faults, allowing precise control of sensing margins and reducing the need for multiple reference cells.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If dual pre-programmed reference cells are used, then reference voltage can be generated, but stuck-at faults and shifting reference values occur reducing reliability

Engineering Contradiction:

Improvereference voltage stabilityVSAvoidreference cell configuration

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the problematic pre-programming step from the reference cell setup. Instead of requiring two reference cells to be pre-programmed to specific states, the invention uses a single reference cell that leverages the native anti-parallel state after magnetic annealing, eliminating the need for complex pre-programming operations and reducing the risk of stuck-at faults

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the operational parameter from requiring pre-programmed binary states to utilizing the native magnetic state after annealing. By adjusting the reference cell to operate in its natural anti-parallel state and using a programmable PMOS load to generate the midpoint voltage, the system achieves reliable reference voltage without the complexity of dual pre-programmed cells

Inventive Principle:

Principle #35Parameter changes

2Reliability

If two reference cells are pre-programmed to '0' and '1' states, then reference voltage is generated, but chip area increases

Engineering Contradiction:

Improvereference voltage generationVSAvoidchip area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges the functions of two separate reference cells into a single reference cell configuration. By combining the reference cell with a programmable PMOS load, the system generates the midpoint reference voltage using only one physical cell, thereby reducing the chip area occupied by reference circuitry while maintaining reliable voltage generation

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The single reference cell is designed to perform multiple functions: it serves as both the reference element and works in conjunction with the programmable PMOS load to generate the midpoint voltage. This multi-functional approach eliminates the need for separate dedicated reference cells for each binary state, reducing overall chip area

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Productivity

If conventional reference circuits are used, then sensing operation is performed, but sensing margins are reduced due to process variations

Engineering Contradiction:

Improvesensing operation speedVSAvoidsensing margin

Core Design Contradiction:

ProductivityVSMeasurement precision

Solution Approach 1:

The patent introduces a feedback mechanism through the programmable PMOS load that allows dynamic adjustment of the reference voltage level. This feedback capability enables the system to compensate for process variations and maintain optimal sensing margins by adjusting the PMOS load programming based on actual device characteristics and environmental conditions

Inventive Principle:

Principle #23Feedback

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach improves yield, sensing margins, and tolerance to process variations, while maintaining the bitcell footprint of conventional reference circuits, reducing errors and costs by eliminating the need for dual pre-programmed reference cells.

Implementation Method 1

Due to the tunnel magnetoresistive effect, the electrical resistance of the MTJ 100 changes based on the orientation of the polarities in the two magnetic layers

Methodology Applied

Scientific EffectTunnel magnetoresistive effect: Magnetoresistance

Implementation Method 2

During the write operation, the spin-polarized electrons exert a torque on the free layer, which can switch the polarity of the free layer

Methodology Applied

Scientific EffectSpin transfer torque:

Implementation Method 3

During the process of magnetic annealing, the wafers are placed in an oven and heated up to temperatures of 400C, while under the influence of a powerful magnetic field. This temperature is maintained for about six hours, which causes the atomic moments to orient in a desired direction, based on the applied magnetic field

Methodology Applied

Scientific EffectMagnetic annealing: Annealing

Data Source

PatentEP2732449B1MRAM sensing with magnetically annealed reference cell

Publication Date: 2019.10.23 QUALCOMM INC

Figure 1A~1B
Figure 2
Figure 3A~3B

AI summary

Systems and method for reading/sensing data stored in magnetoresistive random access memory (MRAM) cells using magnetically annealed reference cells. A MRAM includes a reference circuit (570) comprising at least one magnetic storage cell (506), wherein each magnetic storage cell in the MRAM is programmed to the same state. The reference circuit includes a load element coupled to the magnetic storage cell, wherein the load element (512) is configured to establish a reference voltage during a read operation.