MRAM Data Scrubbing via APVIC Weight Adjustment
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Solution Overview
Problem
Existing MRAM technologies face challenges in optimizing retention properties for LLC applications, leading to error accumulation at higher ambient temperatures and increased sensitivity to magnetic fields, resulting in malfunctions and inefficient data scrubbing that causes unnecessary power consumption and memory wear.
Innovation Solution
The implementation of a data scrubbing circuit in conjunction with an analog persistent vital information circuit (APVIC) that adjusts weights for memory blocks based on a timer, data accesses, and environmental factors like ambient temperature and magnetic field strength, allowing for individual block scrubbing and dynamic threshold adjustment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data scrubbing is performed on the entire memory array, then error correction is achieved, but power consumption and memory wear increase unnecessarily
Solution Approach 1:
The patent divides the memory array into multiple memory blocks and implements data scrubbing on an individual block basis rather than scrubbing the entire array. Each memory block has its own weight counter that tracks error accumulation independently, allowing selective scrubbing only of blocks that meet the scrubbing threshold, thereby reducing unnecessary power consumption and memory wear.
Solution Approach 2:
The patent applies different scrubbing policies to different memory blocks based on their local error accumulation characteristics. Each memory block maintains its own weight counter and is evaluated independently against the scrubbing threshold, enabling localized scrubbing decisions that match the actual error conditions of each block rather than applying a uniform scrubbing approach to the entire array.
2Reliability
If data scrubbing is performed on the entire memory array, then error correction is achieved, but memory wear increases unnecessarily
Solution Approach 1:
The patent segments the memory array into multiple blocks with independent weight counters, allowing scrubbing to be applied selectively to only those blocks that require it. This segmentation prevents unnecessary scrubbing operations on healthy blocks, thereby reducing memory wear and extending the overall memory lifetime while maintaining error correction capability.
Solution Approach 2:
The patent implements partial scrubbing by applying scrubbing operations only to memory blocks that meet the scrubbing threshold condition, rather than performing excessive scrubbing on the entire array. This partial action approach maintains sufficient error correction while minimizing unnecessary write operations that contribute to memory wear.
3Speed
If MRAM retention properties are optimized for LLC applications, then speed and cycling endurance improve, but error accumulation increases at higher ambient temperatures
Solution Approach 1:
The patent implements a feedback mechanism using weight counters for each memory block that monitor error accumulation in real-time. These counters provide feedback about the actual error conditions, enabling the system to dynamically adjust scrubbing frequency and threshold based on observed error rates, thereby maintaining reliability at high temperatures without sacrificing the speed optimizations achieved through relaxed retention properties.
Solution Approach 2:
The patent introduces dynamic adaptability by allowing the data scrubbing threshold to be adjusted based on environmental conditions such as ambient temperature. This dynamic approach enables the system to maintain optimal performance across varying temperature conditions, compensating for increased error accumulation at higher temperatures while preserving the speed benefits of optimized retention properties.
4Duration of action of moving object
If MRAM is optimized for LLC applications, then cycling endurance improves, but sensitivity to magnetic fields increases
Solution Approach 1:
The patent implements self-service through monitoring circuits and weight counters that automatically detect and track error accumulation in each memory block. This self-monitoring capability enables the system to identify and scrub affected blocks without external intervention, maintaining reliability despite increased magnetic field sensitivity while preserving the cycling endurance benefits of LLC optimization.
Data Source
AI summary
Embodiments are disclosed for a system that includes a data scrubbing circuit, a magnetoresistive random access memory (MRAM) having a memory array, and an analog persistent vital information circuit (APVIC) that performs a method. The method includes resetting weights corresponding to blocks of the memory array. The method further includes adjusting the weights based on a timer, data accesses on the memory blocks, and weight change values corresponding to the weights. The method also includes determining, in response to the timer, a data scrubbing threshold based on ambient temperature and magnetic field strength. The method additionally includes determining one of the weights meets the data scrubbing threshold. Further, the method includes providing, in response to the determination, an indication that a data scrubber, scrub one of the memory blocks corresponding to the weight that meets the data scrubbing threshold. Also, the method includes resetting the weight.