MRAM Array Integration with Transistor Source Drain Regions
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing methods for forming magnetoresistive random access memory (MRAM) arrays are inefficient due to the separate formation of MRAM bits and drive/sense circuits, leading to increased manufacturing steps, cost, and chip area usage.
Innovation Solution
Integrating MRAM bits directly with drive/sense transistors on a common semiconductor substrate, reducing the number of vias and metal layers, and forming MRAM bits in close proximity to source/drain regions for improved process and space efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If MRAM bits and drive/sense circuits are formed separately on a common substrate, then each component can be independently optimized, but the total number of manufacturing steps increases and chip area increases
Solution Approach 1:
The patent merges the formation of MRAM bits and drive/sense circuits into a unified manufacturing process. The bit stack structure is formed integrally with the transistor structures on the same substrate, allowing both components to be created simultaneously through shared process steps such as depositing magnetic layers, forming electrode structures, and creating interconnect layers, thereby reducing the total number of manufacturing steps while maintaining independent component functionality
Solution Approach 2:
The patent employs universal process steps that serve multiple functions: the same electrode structures serve as both transistor contacts and MRAM bit electrodes, the same interconnect layers provide both transistor interconnection and bit stack connection, and the same substrate supports both circuit elements. This multi-functionality reduces process complexity while maintaining design flexibility
2Ease of manufacture
If MRAM bits are formed separately from drive/sense circuits, then manufacturing flexibility is maintained, but chip area increases and manufacturing yield decreases
Solution Approach 1:
The patent implements a nested structure where the MRAM bit stack is positioned directly over the source/drain region of the transistor, with the bit stack components nested within the vertical space above the transistor structure. This nesting arrangement eliminates the need for separate lateral spacing and reduces chip area while maintaining manufacturing flexibility through standard semiconductor fabrication processes
3Reliability
If multiple vias and metal layers are used to connect MRAM bits to drive/sense circuits, then connection reliability is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent extracts and eliminates the unnecessary intermediate vias and metal layers from the traditional connection architecture. By directly integrating the bit stack electrode with the transistor source/drain region, the design removes multiple connection interfaces and intermediate structures, thereby reducing device complexity and manufacturing steps while maintaining connection reliability through direct electrical contact
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the complexity and number of manufacturing steps, decreases chip area usage, and enhances manufacturing yield and cost-effectiveness by eliminating unnecessary layers and increasing integration efficiency.
Implementation Method 1
For convenience of description it is assumed that spin momentum transfer is used to program MRAM bit 22
Implementation Method 2
magnetoresistive random access memory (MRAM) bit 22
Data Source
AI summary
Embodiments of a magnetoresistive random access memory (MRAM) array include multiple transistors having source and drain regions, and multiple substantially planar MRAM bits. The MRAM bits have upper and lower electrodes and intervening magnetics layers. The lower electrodes of at least some of the MRAM bits are formed substantially directly on at least some of the source or drain regions without an intervening via. Embodiments of an MRAM array also include a first conductive interconnect layer above and in electrical contact with the upper electrodes of at least some of the MRAM bits, with no metal layers intervening between the upper electrodes and the first conductive interconnect layer.