MRAM Memory Array Layout Combining STT and SOT Writing

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Existing magnetoresistive random access memories (MRAM) face issues such as asymmetric write current directions leading to performance degradation, source degradation, and limited integration density due to the use of STT and SOT technologies.

Innovation Solution

A memory array structure that integrates both STT and SOT effects, reducing the number of transistors and improving write speed and reliability, while enhancing storage density by coupling write transistors to magnetic tunnel junctions with a conductor layer connected to high-level and low-level wirings.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If STT effect is used for magnetic tunnel junction flipping, then the write operation can be performed, but the write speed is limited by inherent flip time delay and performance degrades due to asymmetric write current directions

Engineering Contradiction:

Improvewrite speedVSAvoiddevice reliability

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The patent combines both STT and SOT effects in a single memory cell structure. The write transistor can operate in two modes: applying current through the MTJ for STT effect, or applying current through the conductor layer for SOT effect. This merging allows the system to leverage the speed advantage of SOT while maintaining the simplicity of STT, thereby improving write speed without sacrificing reliability.

Inventive Principle:

Principle #5Merging (Combining)

2Speed

If SOT effect is used for magnetic tunnel junction flipping, then the write speed is improved, but the circuit structure complexity increases due to requiring two access transistors and the problem of source degradation still exists

Engineering Contradiction:

Improvewrite speedVSAvoidcircuit structure complexity

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The patent merges STT and SOT effects within a one-transistor-one-MTJ cell structure. The write transistor is configured to selectively apply write current either through the MTJ (STT mode) or through the conductor layer (SOT mode), eliminating the need for separate write and read transistors required in conventional SOT-MRAM. This reduces circuit complexity while maintaining the high write speed advantage of SOT effect.

Inventive Principle:

Principle #5Merging (Combining)

3Speed

If conventional SOT-MRAM structure with two access transistors is used, then the write speed is improved, but the integration density is difficult to improve due to increased transistor count

Engineering Contradiction:

Improvewrite speedVSAvoidintegration density

Core Design Contradiction:

SpeedVSProductivity

Solution Approach 1:

The patent integrates both STT and SOT functionality into a single transistor-MTJ cell structure. The write transistor serves dual purposes: controlling STT write operations through the MTJ and controlling SOT write operations through the conductor layer. This merging enables high write speed performance while achieving higher integration density by reducing the transistor count per memory cell.

Inventive Principle:

Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The proposed memory array improves write speed, device reliability, and reduces circuit static power consumption while increasing storage density compared to STT-MRAM and SOT-MRAM models.

Implementation Method 1

The MTJ may be in two states, that is, the magnetization directions of the two magnetic layers are parallel (P) or antiparallel (AP) to each other, so that the MTJ is in a low-resistance state or a high-resistance state, which is called a tunnel magnetoresistance effect (TMR).

Methodology Applied

Scientific EffectTunnel magnetoresistance effect: Magnetoresistance

Implementation Method 2

a write operation of which utilizes the spin transfer torque effect to flip the magnetization direction of the free magnetic layer

Methodology Applied

Scientific EffectSpin transfer torque effect:

Implementation Method 3

current flowing through the heavy metal or the antiferromagnetic layer can induce a torque to flip the magnetization direction of the free layer of the MTJ to realize a magnetic write

Methodology Applied

Scientific EffectSpin orbit torque effect:

Data Source

PatentUS12432938B2Memory array, memory, preparing method and writing method

Publication Date: 2025.09.30 BEIHANG UNIV

AI summary

Disclosed are a memory array, a memory, a preparing method and a writing method. Some embodiments relate to a memory array for a magnetoresistive random access memory and a manufacturing method thereof. The memory array includes: a plurality of memory cells arranged in an array and a conductor layer; each of the memory cells includes: a write transistor, a first end of which is coupled to top electrode wiring; a magnetic tunnel junction MTJ, one end of which close to a reference layer is coupled to a second end of the write transistor; a side surface of the conductor layer is coupled to end faces of one end of all of the magnetic tunnel junctions MTJs close to a free layer.