MRAM Bank Segmentation for DDR Controller Compatibility
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Solution Overview
Problem
Conventional MRAM and DRAM systems are incompatible due to differences in write current, page size, and operational requirements, preventing systems with DRAM controllers from utilizing the benefits of MRAM memory.
Innovation Solution
A memory device with a plurality of read/write pipelines and an engine to control these pipelines, allowing simultaneous processing of read and write operations across multiple banks, enabling coordination with DDR interfaces and accommodating different memory types like MRAM and DRAM.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional MRAM uses smaller page sizes, then write current requirements are reduced, but compatibility with DDR DRAM controllers is lost
Solution Approach 1:
The memory system is divided into multiple independent banks, each capable of handling operations autonomously. This segmentation allows the MRAM to present a DDR-compatible interface at the bank level while maintaining efficient smaller page sizes within each bank, resolving the compatibility issue without sacrificing energy efficiency.
Solution Approach 2:
The MRAM device is designed to perform multiple functions: it can operate with smaller page sizes for efficient write current usage, while simultaneously presenting a DDR-compatible interface to external controllers. The multi-functional design includes support for both traditional MRAM operations and DDR memory protocols, enabling universal compatibility.
2Adaptability or versatility
If conventional MRAM uses larger page sizes to match DRAM, then compatibility with DDR interfaces is improved, but write current requirements increase
Solution Approach 1:
The memory is organized into multiple banks where each bank can independently manage its own page size. This allows the system to present larger effective page sizes to DDR controllers through bank aggregation while individual banks maintain smaller page sizes that require lower write currents, thus resolving the contradiction between compatibility and energy consumption.
3Productivity
If multiple read/write pipelines are used to process operations simultaneously, then productivity increases, but device complexity increases
Solution Approach 1:
The memory system is divided into multiple independent banks, each with its own read/write pipeline. This segmentation allows parallel processing of operations across different banks, increasing productivity. The independence of each bank simplifies the control logic compared to a fully integrated complex pipeline, as each bank can operate autonomously with standardized control signals.
Solution Approach 2:
Multiple independent bank pipelines are merged at the controller level to present a unified DDR-compatible interface. This combining approach allows the system to achieve high throughput through parallel bank operations while maintaining a relatively simple control structure at each bank, resolving the contradiction between productivity and complexity.
Data Source
AI summary
Embodiments of the present invention facilitate efficient and effective increased memory cell density configuration. In one embodiment, a memory system comprises: an array of addressable memory cells, wherein the addressable memory cells of the array comprise magnetic random access memory (MRAM) cells and wherein further the array is organized into a plurality of banks; an engine configured to control access to the addressable memory cells organized into the plurality of banks; and a pipeline configured to perform access control and communication operations between the engine and the array of addressable memory cells. At least a portion of operations associated with accessing at least a portion of one of the plurality of memory banks via the pipeline are performed substantially concurrently or in parallel with at least a portion of operations associated with accessing at least another portion of one of the plurality of memory banks via the pipeline.