MRAM BEOL Structure With Additional Metal Layer for Uniform Via Etching

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Solution Overview

Problem

The variability in via depths for via plugs between magnetoresistive random access memory (MRAM) and other semiconductor devices in BEOL processes leads to uneven etch profiles and excessive etching, causing issues like penetrated regions and reduced yield in integrated circuits.

Innovation Solution

The introduction of an additional metal layer, a bottom electrode, or a cap layer in the MRAM structure ensures uniform etching depths by making the upper via plugs' surfaces coplanar with the dielectric layer, thereby reducing the need for excessive etching and addressing abnormal profiles and open phenomena.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If via plugs are etched to different depths to connect MRAM and other semiconductor devices, then electrical connection is achieved, but etch profiles become uneven and penetrated regions occur

Engineering Contradiction:

Improveelectrical connectionVSAvoidetch profile uniformity

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

An additional metal layer is formed in the MRAM region before the common etching process. This preliminary structure ensures that when etching occurs, both MRAM and non-MRAM regions etch to the same depth to reach the additional metal layer, achieving uniform etch profiles while maintaining proper electrical connections

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The additional metal layer is selectively formed only in the MRAM region, creating local structural differentiation. This allows the MRAM region to have a different etching target depth compared to non-MRAM regions, resolving the conflict between varying via depth requirements and etch profile uniformity

Inventive Principle:

Principle #3Local quality

2Reliability

If excessive etching is performed to ensure connection in all regions, then via plugs connect to lower metal layers, but penetrated regions (opens) occur

Engineering Contradiction:

Improvevia plug connectionVSAvoidpenetrated region

Core Design Contradiction:

ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The additional metal layer is formed in advance in the MRAM region, serving as a predetermined etching stop layer. This prevents excessive etching that would cause penetrated regions, while still ensuring that via plugs achieve proper electrical connection to the lower metal layers through the controlled etching depth

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS20250372512A1Magnetoresistive random access memory BEOL structure improvement for process healthy and yield increase

Publication Date: 2025.12.04 UNITED MICROELECTRONICS CORP

AI summary

A magnetoresistive random access memory includes: a lower metal layer and a lower dielectric layer, disposed on a semiconductor substrate, and the lower metal layer disposed in the lower dielectric layer; a dielectric layer, disposed on the lower dielectric layer and the lower metal layer; a via plug, a magnetic tunnel junction and an additional metal layer, disposed in the dielectric layer, wherein the via plug is electrically connected to the lower metal layer, the magnetic tunnel junction is disposed on the via plug and the additional metal layer is disposed on the magnetic tunnel junction; an upper dielectric layer, disposed on the dielectric layer and the additional metal layer; and an upper via plug and an upper metal layer, disposed in the upper dielectric layer, wherein the upper via plug is electrically connected to the additional metal layer.