MRAM Bit Cell Design with Overlapping Source and Bit Lines
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Solution Overview
Problem
Conventional MRAM bit cell designs are limited by metal and via spacing rules, preventing reduction in bit cell size due to the lack of direct and parallel overlap between source lines and bit lines.
Innovation Solution
The MRAM bit cell design includes placing a portion of the source line on top of the bit line, utilizing via interconnects and a top thin metal layer to achieve direct overlap, thereby overcoming conventional spacing limitations and reducing bit cell size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If source lines are arranged parallel to bit lines following conventional spacing rules, then manufacturing is simplified, but bit cell size cannot be reduced
Solution Approach 1:
The source line is positioned in a different vertical dimension (upper metal layer) relative to the bit line (lower metal layer), enabling direct overlap in the planar view. This vertical separation allows the source line to be placed directly above the bit line without violating conventional metal spacing rules, thereby reducing the bit cell area while maintaining manufacturing compliance.
Solution Approach 2:
The source line is nested within the vertical space above the bit line, with the source line positioned in an upper metal layer and the bit line in a lower metal layer. This nesting arrangement allows the source line to overlap the bit line horizontally while maintaining proper vertical spacing, effectively reducing the bit cell footprint.
2Area of stationary object
If direct overlap between source line and bit line is implemented, then bit cell size is reduced, but metal layer complexity increases
Solution Approach 1:
By utilizing vertical dimension separation, the source line is placed in an upper metal layer while the bit line remains in a lower metal layer. This dimensional separation enables direct horizontal overlap to reduce bit cell area without creating electrical short circuits, as the layers are electrically isolated by the dielectric material between them.
Solution Approach 2:
The dielectric layer between the upper metal layer (source line) and lower metal layer (bit line) acts as an intermediary that prevents electrical interaction while allowing spatial overlap. This mediator enables the source line and bit line to occupy the same horizontal footprint without causing electrical short circuits.
Data Source
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AI summary
Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) bit cells are disclosed. The bit cells include a source line formed in a first plane and a bit line formed in a second plane. The bit line has a longitudinal axis that is parallel to a longitudinal axis of the source line, and the source line overlaps at least a portion of the bit line.