3T2J MRAM Bit Cell with Shared Pass Gate Transistors
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Solution Overview
Problem
Existing MRAM bit cell designs require additional circuitry and complexity for generating reference voltages during read operations and have large pass gate transistors that determine the overall size of the memory cell, leading to inefficiencies in current handling and size constraints.
Innovation Solution
A three-transistor two-junction (3T2J) MRAM bit cell design with two magnetic tunnel junctions (MTJs) connected through a pass gate assembly, where three n-type metal-oxide-semiconductor transistors share the current to change the resistive state of both MTJs, reducing the size of each transistor and eliminating the need for additional circuitry to generate reference currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a first MRAM bit cell includes an MTJ connected to a bit line and a pass gate transistor, then the MTJ can be selectively connected to a source line, but additional circuitry and complexity are required to generate reference voltage for read operations
Solution Approach 1:
The patent combines the reference voltage generation function with the existing bit cell structure by using the second MTJ and shared pass gate transistor to generate reference voltage during read operations, eliminating the need for separate reference voltage generation circuitry
Solution Approach 2:
The second MTJ serves multiple functions: it stores data in the differential bit cell and simultaneously provides reference voltage during read operations, making the component universal and reducing overall circuit complexity
2Reliability
If two pass gate transistors are used to handle the entire current necessary to flip the free layer of each MTJ, then robust current handling is achieved, but the size of the pass gate transistors increases the overall size of the MRAM bit cell
Solution Approach 1:
The patent segments the current handling function by introducing multiple transistor paths (first and second transistor assemblies) that share the current load, allowing each individual transistor to be smaller while collectively handling the full write current
Solution Approach 2:
The patent uses partial action by having multiple transistor assemblies that can handle portions of the write current, where the combined capability of all transistors equals the full current requirement, but each individual transistor operates at reduced capacity
3Area of stationary object
If three n-type metal-oxide-semiconductor transistors share the current to change the resistive state of both MTJs, then the size of each transistor is reduced, but current sharing coordination is required
Solution Approach 1:
The patent divides the write current into multiple parallel paths through first and second transistor assemblies, with each assembly containing transistors that handle portions of the total current, reducing individual transistor size requirements
Solution Approach 2:
The patent employs asymmetric transistor sizing within the assemblies, where transistors are optimized for their specific current handling roles rather than being uniform, allowing more efficient current distribution and smaller overall device footprint
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces the size of the pass gate assembly and overall MRAM bit cell by 25%, minimizes current leakage, and enhances read operation speed and accuracy by allowing a larger current difference to be detected, eliminating the need for external reference current generation and reducing parasitic currents.
Implementation Method 1
Magnetoresistive random access memory (MRAM) uses magnetic tunnel junctions (MTJs) to store data. An MTJ includes a pinned layer and a free layer separated by a dielectric layer. A relative orientation of the pinned layer and the free layer determines a resistance of the MTJ.
Implementation Method 2
The direction of the free layer is set by passing a high current through the MTJ. The direction of the current determines the orientation of the free layer.
Data Source
AI summary
A MRAM bit cell including a first magnetic tunnel junction (MTJ) connected to a first data line and a second MTJ connected to a second data line. The MRAM bit cell further includes a first transistor having a first terminal connected to the first MTJ and a second terminal connected to the second MTJ. The MRAM bit cell further includes a second transistor having a first terminal connected to a driving line and a second terminal connected to the first MTJ. The MRAM bit cell further includes a third transistor having a first terminal connected to the driving line and a second terminal connected to the second MTJ. A method of using the MRAM bit cell is also described.