MRAM Bit Line Write Control Using Source Follower
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Solution Overview
Problem
Accurate power delivery for writing in large magnetoresistive random access memory (MRAM) arrays is challenging due to high power requirements and significant IR drops caused by distributed switches, which complicates regulator response and signal sensing.
Innovation Solution
An MRAM bit line write control circuit is introduced, utilizing a source follower transistor in the bit line decode path and high voltage NFETs to manage voltage across MTJ cells, allowing for efficient write operations without the need for high accuracy, high current regulators, and reducing IR drops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If distributed switches are used to write MTJ devices in parallel, then write capability is improved, but IR drop and power delivery accuracy deteriorate
Solution Approach 1:
A source follower transistor is introduced as an intermediary device between the bit line and the MTJ cell. This source follower acts as a buffer that isolates the bit line from direct connection to multiple MTJ cells, thereby preventing the summation of currents from causing significant IR drops while still enabling parallel write operations to multiple cells.
2Quantity of substance
If array size is increased, then memory capacity is improved, but IR drop and regulator response complexity worsen
Solution Approach 1:
The bit line write control is segmented into individual source follower transistors for each bit line, rather than using a centralized distributed switch control. This segmentation allows each bit line to be independently controlled and isolated, preventing the cumulative IR drops that would occur in a large parallel array while maintaining the ability to scale memory capacity.
3Productivity
If high power is delivered to write MTJ devices, then write efficiency is improved, but power delivery control and IR drop worsen
Solution Approach 1:
The source follower transistor serves as an intermediary that enables high power delivery to selected MTJ cells while isolating the power delivery path. By using the source follower's inherent current limiting and isolation properties, high write currents can be delivered to individual cells without causing cumulative IR drops across the entire bit line, thus maintaining write efficiency while reducing energy loss.
Data Source
AI summary
An MRAM bitline write control circuit including an MRAM array of a plurality of MTJ cells. Each MTJ cell is connected to a bitline between a bitline transfer gate and a transfer device. Each transfer device is connected to a sourceline and a sourceline transfer gate. A master bitline is connected to each bitline transfer gate. A first bitline control transistor is connected to VDD and to a source follower transistor that is connected to the master bitline and a gate connected to a write 0 bias voltage. A second bitline control transistor is connected to VSS and to the master bitline. A selected MTJ cell is biased to write a 0 when the transfer device, the bitline transfer gate and the source line transfer gate, associated with the selected MTJ cell, are enabled and the first bitline control transistor is enabled to connect the source follower transistor to VDD.