MRAM Bit Line Termination for Write Current Stability

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Solution Overview

Problem

In magnetic random access memory (MRAM) using 2T1MTJ cells, it is challenging to stably supply a sufficient write current to memory cells without increasing the area of the memory cell or array, especially as bit capacity increases, due to parasitic resistances in bit lines which attenuate the write current.

Innovation Solution

The implementation of a terminating unit between memory cells and bit lines, which grounds the write current after it passes through the selection cell, reduces parasitic resistance and allows for efficient write current supply by directing the current to termination circuits, thereby minimizing the impact of bit line resistances.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the number of word lines is increased to double the bit capacity, then the memory array area increases, but the parasitic resistance in bit lines increases causing write current attenuation

Engineering Contradiction:
Improvebit capacityVSAvoidparasitic resistance
Core Design Contradiction:
Quantity of substanceVSObject-affected harmful factors

Solution Approach 1:

The patent divides the bit line into multiple segments by introducing terminating units at different positions along the bit line. Each segment serves a specific region of memory cells, reducing the effective resistance for write current supply to each segment while maintaining overall high bit capacity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The terminating unit acts as an intermediary component between the bit line and ground. It provides a controlled path to ground that reduces the parasitic resistance effect on write current by creating intermediate connection points, thereby improving current supply efficiency without increasing area.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If terminating units are added to reduce parasitic resistance, then write current supply efficiency improves, but device complexity increases

Engineering Contradiction:
Improvewrite current supply stabilityVSAvoidcircuit structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The terminating units are selectively placed at specific positions along the bit line where parasitic resistance effects are most significant. This localized approach improves write current supply stability in critical regions while minimizing the overall increase in device complexity.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent modifies the electrical parameters of the bit line by introducing controlled ground connection points through terminating units. This changes the resistance distribution along the bit line, improving current supply stability without requiring fundamental redesign of the overall circuit architecture.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables stable and efficient supply of write current to memory cells, doubling the number of word lines that can be handled without increasing the memory array area, effectively doubling the bit capacity while maintaining low parasitic resistance.

Implementation Method 1

one-bit storage information is assigned to the relative magnetization state between the pinned magnetic layer and the free magnetic layer... the reading from the MRAM is executed by using the fact that the MTJ resistance is different based on the magnetization state

Methodology Applied
Scientific EffectMagnetoresistance: Magnetoresistance

Implementation Method 2

The magnetization of the free magnetic layer is switched in a desirable direction by the synthesis magnetic field generated by the respective write currents

Methodology Applied
Scientific EffectElectromagnetic field generation: Electromagnetic Induction

Data Source

PatentUS7773405B2Magnetic random access memory and operating method of magnetic random access memory
Publication Date: 2010.08.10 NEC CORP
  • US7773405B2 patent drawing
  • US7773405B2 patent drawing
  • US7773405B2 patent drawing

AI summary

A magnetic random access memory includes: a first and second wirings, a plurality of third wirings, a plurality of memory cells and a terminating unit. The first and second wirings extend in a Y direction. The plurality of third wirings extends in an X direction. The memory cell is provided correspondingly to an intersection between the first and second wirings and the third wiring. The terminating unit is provided between the plurality of memory cells and connected to the first and second wirings. The memory cell includes transistors and a magnetoresistive element. The transistors are connected in series between the first and second wirings and controlled based on a signal of the third wiring. The magnetoresistive element is connected to a wiring through which the transistors are connected. At a time of a writing operation, when the write current 1w is supplied from one of the first and second wiring to the other through the transistors, the terminating unit grounds the other.