MRAM Bit Cell Inversion for Shorted Cell Error Correction
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Solution Overview
Problem
Magnetic random access memory (MRAM) devices experience higher bit error rates due to dielectric breakdown of magnetic tunnel junctions, limiting their endurance and lifetime, and existing error correction circuits struggle to correct errors introduced by shorted bit cells.
Innovation Solution
Incorporating a short detection circuit and error correction mechanisms, such as majority detection and inversion schemes, to identify and compensate for shorted bit cells before data output, thereby extending the memory device's usable lifetime and reducing error rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If magnetic tunnel junctions are used to store data in MRAM devices, then data storage capability is achieved, but dielectric breakdown occurs leading to higher bit error rates and reduced device lifetime
Solution Approach 1:
The patent applies preliminary action by detecting shorted bit cells before they cause data errors. The detection circuit identifies compromised MTJs in advance, allowing the system to compensate for them during write operations by inverting data bits stored in those locations. This preventive approach prevents errors from occurring in the first place, thereby maintaining reliability while extending device lifetime.
2Reliability
If error correction circuits are used to correct errors from shorted bit cells, then bit error rate is reduced, but the circuits cannot correct multiple errors within the same ECC word
Solution Approach 1:
The patent performs preliminary detection and identification of shorted bit cells before error correction is attempted. By knowing in advance which MTJs are compromised, the system can pre-invert data bits at those locations during the write operation. This ensures that when data is read later, the ECC circuit only needs to handle natural bit flips rather than errors caused by shorted cells, enabling correction of multiple errors within the same ECC word.
Solution Approach 2:
The patent converts the harmful effect of shorted bit cells into a beneficial mechanism by using the known locations of compromised MTJs to guide data inversion. Instead of treating shorted cells as mere errors to be corrected, the system proactively inverts data at those locations during writing, transforming the potential harm into a controlled and manageable condition that works in conjunction with ECC circuits.
3Duration of action of stationary object
If short detection and inversion mechanisms are implemented, then device lifetime is extended, but detection precision is required to identify shorted cells accurately
Solution Approach 1:
The patent introduces an intermediary detection circuit that mediates between the physical state of MTJs and the data storage system. This circuit uses voltage threshold comparisons to indirectly identify shorted bit cells without requiring direct measurement of each MTJ's resistance. By using voltage thresholds as an intermediary metric, the system achieves sufficient detection accuracy to distinguish shorted cells from functional ones, enabling lifetime extension without demanding extreme measurement precision.
Data Source
AI summary
In some examples, a memory device may be configured to store data in either an original or an inverted state based at least in part on a state associated with one or more shorted bit cells. For instance, the memory device may be configured to identify a shorted bit cell within a memory array and to store the data in the memory array, such that a state of the data bit stored in the shorted bit cell matches the state associated with the shorted bit cell.