MRAM Bottom Electrode with Conductive Metal Plug
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Solution Overview
Problem
Current magnetoresistive random-access memory (MRAM) technologies face challenges in integrating a bottom electrode with low sheet resistance and low contact resistance within the CMOS BEOL process, affecting the electrical performance of magnetic tunnel junction (MTJ) stacks.
Innovation Solution
A method involving the formation of a lower electrode with a conductive metal plug, aligned perpendicularly to the semiconductor substrate, which includes a barrier layer, a liner layer, and a tantalum-containing layer, coupled with a MTJ stack to reduce film resistance and contact resistance, improving electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a bi-layer extended bottom electrode (e.g., tantalum nitride/tantalum) is used in conventional MRAM structures, then the MTJ stack can be integrated into the CMOS BEOL process, but the electrode exhibits relatively high sheet resistance and high contact resistance, degrading electrical performance
Solution Approach 1:
The bottom electrode is segmented into multiple functional layers: a conductive metal plug layer (copper or copper alloy) for low resistance, a barrier layer (tantalum nitride or tungsten nitride) for diffusion prevention, and a liner layer (tantalum or tungsten) for adhesion. This segmentation allows each layer to optimize its specific function, achieving low sheet resistance and contact resistance while maintaining manufacturability in CMOS BEOL processes
Solution Approach 2:
The bottom electrode uses composite material structure combining copper (or copper alloy) with tantalum nitride/tungsten nitride barriers and tantalum/tungsten liners. This composite approach leverages the high conductivity of copper while using the barrier and liner materials to prevent diffusion and ensure adhesion, resolving the contradiction between electrical performance and manufacturing ease
2Speed
If the bottom electrode sheet resistance and contact resistance are reduced to improve electrical performance, then MRAM device speed and reliability improve, but the fabrication process complexity increases
Solution Approach 1:
The invention changes the material parameters of the bottom electrode by using copper (or copper alloy) with resistivity less than 2.0 micro-ohm centimeters, and optimizes the thickness parameters of each layer (conductive plug, barrier, and liner layers) to achieve low sheet resistance and contact resistance. These parameter optimizations enable fast device operation while keeping the fabrication process compatible with standard CMOS BEOL techniques
3Reliability
If a conductive metal plug with barrier and liner layers is used to reduce resistance, then sheet resistance and contact resistance decrease, but the number of fabrication steps increases
Solution Approach 1:
The barrier layer and liner layer are deposited in advance before forming the conductive metal plug. This preliminary action prevents diffusion issues and adhesion problems before they occur, ensuring low resistance and high reliability. The sequence is optimized to be compatible with CMOS BEOL process flow, minimizing impact on fabrication throughput while achieving the desired electrical performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach results in a lower electrode with reduced film resistance and contact resistance, enhancing the electrical performance of the MTJ/MRAM application compared to conventional extended bottom electrodes.
Implementation Method 1
The lower electrode includes a conductive metal plug... reduced film resistance and contact resistance, improving electrical performance
Data Source
AI summary
Integrated circuits that include a magnetic tunnel junction (MTJ) for a magnetoresistive random-access memory (MRAM) and methods for fabricating such integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a lower electrode on a metal interconnect. The metal interconnect is disposed above a semiconductor substrate and is aligned with a normal axis that is substantially perpendicular to the semiconductor substrate. The lower electrode includes a conductive metal plug. A MTJ stack is formed on the lower electrode aligned with the normal axis.