MRAM Multiple-Part Bottom Electrode for Void-Free Inter-Pillar ILD
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Solution Overview
Problem
The challenge in fabricating MRAM devices lies in forming inter-pillar spaces with inter-layer dielectric (ILD) that are void-free, which can lead to shorts and hinder scalability and performance due to the presence of voids in the ILD between pillars.
Innovation Solution
A multi-level bottom electrode structure is employed, with each electrode pad having a greater width than height, and a bottom electrode pillar with a height greater than width, combined with an outwardly tapered vertical side surface for the MTJ stack layers, ensuring void-free ILD fill and reduced shorts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional bottom electrode structure is used, then manufacturing is simpler, but ILD voiding occurs leading to shorts and reduced reliability
Solution Approach 1:
The bottom electrode is segmented into multiple pads (first bottom electrode pad, second bottom electrode pad, third bottom electrode pad) arranged at different levels and positions. This segmentation allows each pad to be optimized for its specific function and enables better control over ILD filling in the inter-pillar spaces, eliminating voids and preventing shorts.
Solution Approach 2:
The bottom electrode structure transitions from a single-level planar configuration to a multi-level three-dimensional arrangement. The pads are positioned at different vertical levels and horizontal positions, creating a stepped configuration that improves ILD fillability and eliminates voids in the inter-pillar regions.
2Manufacturing precision
If multi-level bottom electrode structure is used, then ILD voiding is reduced, but manufacturing complexity increases
Solution Approach 1:
The multi-level bottom electrode pads are formed in advance before the MTJ stack layers are deposited. This preliminary formation establishes the precise geometric framework that guides subsequent material deposition and defines the exact geometry of the inter-pillar spaces, ensuring void-free ILD filling in later manufacturing steps.
Solution Approach 2:
Each bottom electrode pad is designed with specific local dimensions and positions optimized for its particular role. The first, second, and third pads have different widths and heights tailored to their specific locations, allowing precise control over ILD filling in each local region while maintaining overall structural integrity.
3Ease of operation
If tapered side surfaces are used for MTJ stack layers, then connectivity between wirings is improved, but device complexity increases
Solution Approach 1:
The MTJ stack layers are given asymmetric tapered side surfaces rather than symmetric cylindrical or rectangular profiles. The side surfaces are tapered at specific angles to create a gradual expansion from the bottom electrode pads upward, which facilitates smooth connectivity between lower and upper level wirings while avoiding abrupt geometric changes that would increase manufacturing complexity.
Data Source
AI summary
A semiconductor device including a magnetic tunnel junction (MTJ) stack having a bottom electrode, where the bottom electrode includes a first bottom electrode pad and a bottom electrode pillar. A MTJ stack including vertically aligned layers of a top electrode, a free layer, a tunneling barrier, a reference layer and a bottom electrode, where the top electrode includes a tapered side surface having a width at an upper surface of the top electrode greater than a width at a lower surface of the top electrode, and the bottom electrode includes a first bottom electrode pad and a bottom electrode pillar. A MTJ stack, the MTJ stack having a bottom electrode, where the bottom electrode includes a bottom electrode pillar on a first bottom electrode pad on a second bottom electrode pad on a third bottom electrode pad.