MRAM Buffer Memory Segmentation for Storage Speed and Power Trade-offs

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Solution Overview

Problem

Existing storage devices face challenges in achieving high-speed and low-power operations while maintaining product reliability, especially as magnetic memory devices become increasingly highly integrated.

Innovation Solution

The storage device incorporates a first and second buffer memory with MRAM cells operating at different parameters, such as writing speed, and a non-volatile memory, with a storage controller managing data storage between these components based on data volume.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a single buffer memory with fixed operation parameters is used, then the device structure is simple, but the speed and power efficiency cannot be optimized for different workloads

Engineering Contradiction:
Improvewriting speedVSAvoidbuffer memory configuration
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The buffer memory is divided into multiple independent buffer memories (first buffer memory and second buffer memory), each with different operation parameters. This segmentation allows the system to select the appropriate buffer based on workload requirements, achieving both speed optimization and structured complexity.

Inventive Principle:
Principle #1Segmentation

2Productivity

If MRAM cells operate at high writing speed, then data storage performance is improved, but power consumption increases

Engineering Contradiction:
Improvedata storage efficiencyVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

Different buffer memories are assigned different operation parameters tailored to specific workload characteristics. The first buffer memory operates at parameters optimized for certain conditions while the second buffer memory operates at parameters optimized for other conditions, allowing local optimization of both speed and power consumption based on actual usage patterns.

Inventive Principle:
Principle #3Local quality

3Productivity

If buffer memory operations are highly optimized for speed, then data processing efficiency is improved, but product reliability may be compromised

Engineering Contradiction:
Improveoperation speedVSAvoidproduct reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The system changes operation parameters (such as writing speed, voltage levels, or timing characteristics) between different buffer memories to balance speed and reliability requirements. By having multiple buffers with different parameter sets, the system can select the appropriate buffer that meets both performance and reliability criteria for each specific operation.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enhances the storage device's speed and reliability by optimizing buffer memory operations and data storage management, thereby improving overall performance and product reliability.

Implementation Method 1

spin transfer torque-magnetoresistive random access memory (STT-MRAM) for storing information using a spin transfer torque (STT) phenomenon is being studied. The STT-MRAM may induce a magnetization reversal by applying a direct current to a magnetic tunnel junction element, thereby storing information.

Methodology Applied
Scientific EffectSpin transfer torque (STT):

Data Source

PatentUS20250190118A1Storage device
Publication Date: 2025.06.12 SAMSUNG ELECTRONICS CO LTD
  • US20250190118A1 patent drawing
  • US20250190118A1 patent drawing
  • US20250190118A1 patent drawing

AI summary

A storage device includes a first buffer memory and a second buffer memory that are different from each other in at least one operation parameter, a non-volatile memory, and a storage controller connected to the first buffer memory, the second buffer memory, and the non-volatile memory and configured to perform communication with the first buffer memory, the second buffer memory and the non-volatile memory. Each of the first buffer memory and the second buffer memory includes Magnetic Random Access Memory (MRAM) cells and a peripheral circuit configured to operate the MRAM cells according to the at least one operation parameter.