MRAM Burst Write Interface with Mask Register Control
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Solution Overview
Problem
Magnetic random access memory (MRAM) and spin torque transfer MRAM (STTMRAM) suffer from slower write operations compared to static random access memory (SRAM), even in burst modes, which hampers their performance in memory applications.
Innovation Solution
A memory device with a magnetic memory unit that performs burst write operations across multiple clock cycles, utilizing a mask register to inhibit or enable data units during write operations, allowing concurrent read and write operations and emulating a DRAM-like interface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If MRAM/STTMRAM performs write operations using conventional methods, then data can be stored in magnetic memory units, but the write operation speed is slower compared to SRAM
Solution Approach 1:
The patent segments the write operation into multiple independent clock cycles, allowing different data units to be written at different times. The memory unit can accept a burst of data where each data unit is written in sequence during multiple clock cycles, rather than requiring all data to be written simultaneously or sequentially in a single operation cycle.
Solution Approach 2:
The patent implements preliminary action by allowing the memory device to receive and buffer data units in advance during the burst write operation. The mask register is prepared with enable/disable patterns before the actual write to the magnetic memory units occurs, allowing the system to optimize the write timing and reduce overall write operation time.
2Speed
If MRAM/STTMRAM performs burst write operations to improve speed, then write operation speed improves compared to single data writes, but write operations still take longer than read operations
Solution Approach 1:
The patent ensures continuity of useful action by allowing the memory device to continuously receive data units during the burst write operation across multiple clock cycles without idle periods. The mask register continuously generates enable patterns for each data unit, and the magnetic memory units continuously update their state, maximizing the utilization of the write pathway throughout the operation.
Solution Approach 2:
The patent implements dynamics by making the mask register contents configurable and changeable for each burst write operation. The mask patterns can be dynamically adjusted to enable or disable specific data units based on the operation requirements, allowing flexible optimization of write performance for different data patterns and access modes.
3Productivity
If MRAM/STTMRAM allows concurrent read and write operations, then overall system throughput improves, but operation complexity increases
Solution Approach 1:
The patent segments the memory unit into multiple independent magnetic memory units that can operate independently. Each memory unit can perform read or write operations independently, allowing concurrent operations across different units. The mask register is also segmented to control each data unit independently, enabling fine-grained control of concurrent operations.
Solution Approach 2:
The mask register acts as an intermediary between the data input and the magnetic memory units during write operations. It mediates which data units are written by generating enable patterns, while read operations can proceed independently from other memory units. This intermediary structure allows concurrent read and write operations without direct conflict.
Data Source
AI summary
A memory device includes a magnetic memory unit for storing a burst of data during a burst write operation. Each burst of data includes sequential data units with each data unit being received at a clock cycle, and written during the burst write operation, wherein the burst write operation is performed during multiple clock cycles. Further, the memory device includes a mask register coupled to the magnetic memory unit that generates a write mask during the burst write operation to inhibit or enable data units of write data. Furthermore, the memory device allows a next burst write operation to begin while receiving data units of the burst of data to be written or providing read data.