MRAM Top Electrode Capping Structure for Lower Interconnect Resistance
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Solution Overview
Problem
The integration of MRAMs in BEOL processes face challenges in existing technologies have not effectively addressed the increased height of the MRAM stack, leading to increased BEOL interconnect resistance, which hinders efficient integration of MRAM bit cells in semiconductor storage devices.
Innovation Solution
A memory device design where a top electrode is electrically connected to a conductive interconnect through a metal capping layer, with the conductive interconnect located on opposite sidewalls of the metal capping layer, ensuring a coplanar top surface with the conductive interconnect, thereby reducing the height of the MRAM stack and minimizing interconnect resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the MRAM stack height is increased to accommodate the magnetic tunnel junction and electrode structures, then the data storage capability is improved, but the BEOL interconnect resistance increases
Solution Approach 1:
The patent transitions from a vertical interconnect architecture to a lateral interconnect architecture. The metal capping layer extends laterally from the top electrode to the conductive interconnect, allowing electrical connection without increasing vertical stack height. This dimensional change enables the interconnect to bypass the height issue while maintaining electrical functionality.
Solution Approach 2:
The metal capping layer serves as an intermediary element that bridges the top electrode and the conductive interconnect. It provides a low-resistance electrical pathway while physically connecting components that would otherwise be difficult to connect without increasing stack height, thus resolving both the electrical connection requirement and the height constraint.
2Reliability
If the MRAM stack height is increased to ensure proper electrode connection, then the electrical connection reliability is improved, but the integration density in BEOL processes deteriorates
Solution Approach 1:
The invention moves the interconnect path from the vertical dimension to the lateral dimension. By extending the metal capping layer horizontally from the top electrode to the conductive interconnect, the design maintains electrical connection reliability without consuming additional vertical space, thereby preserving integration density in the BEOL process.
Solution Approach 2:
The metal capping layer functions as a thin film that provides electrical connection while occupying minimal volume. This thin film approach allows the interconnect to be formed without significantly increasing the overall device footprint, maintaining high integration density while ensuring reliable electrical connection.
3Ease of manufacture
If a traditional vertical interconnect structure is used, then the manufacturing process is simpler, but the interconnect resistance increases due to longer current path
Solution Approach 1:
The patent shortens the current path by transitioning from a vertical interconnect configuration to a lateral one. The metal capping layer creates a direct horizontal pathway from the top electrode to the conductive interconnect, reducing the current path length and associated resistance while remaining compatible with standard BEOL manufacturing processes.
Data Source
AI summary
A magneto-resistive random access memory device includes a top electrode electrically connected to a conductive interconnect through a metal capping layer located above a top surface and opposite sidewalls of the top electrode, the conductive interconnect is located on opposite sidewalls of the metal capping layer with a top surface of the metal capping layer being coplanar with a top surface of the conductive interconnect.