MRAM Cell Architecture for 6F2 Miniaturization
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Solution Overview
Problem
Magnetic random access memory (MRAM) has a larger cell size compared to DRAM, which is a limitation for its potential as a DRAM substitute due to increased wiring, making it desirable to achieve a cell size of 6F2 for improved efficiency and miniaturization.
Innovation Solution
The design includes a semiconductor memory device with word lines and bit lines arranged in a specific configuration, featuring variable resistance elements, select transistors, and contact plugs, allowing for a 6F2 cell size by aligning MTJ elements and contact plugs between word lines and bit lines, and using the spin-transfer torque writing method to control magnetization states for data storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If MRAM uses traditional wiring configuration, then data storage function is achieved, but cell size becomes larger than DRAM
Solution Approach 1:
The patent introduces a third bit line (BL3) in addition to the conventional two bit lines, creating a three-dimensional wiring architecture. This dimensional expansion allows for more efficient routing and reduces the planar footprint of the memory cell, enabling 6F2 cell size achievement while maintaining necessary connectivity for spin-transfer torque writing operations
2Area of moving object
If MRAM achieves 6F2 cell size, then miniaturization is improved, but wiring resistance and parasitic capacitance increase
Solution Approach 1:
The patent optimizes the wiring configuration locally by strategically positioning the three bit lines and variable resistance elements. The bit lines are arranged to minimize overlapping and parasitic capacitance, while the variable resistance elements are positioned to reduce current path length. This localized optimization reduces wiring resistance and parasitic effects despite the compact 6F2 cell size
3Ease of operation
If three bit lines are used for spin-transfer torque writing, then data writing capability is improved, but manufacturing complexity increases
Solution Approach 1:
The three bit lines (BL1, BL2, BL3) are designed with universal functionality where any combination can serve as write or read lines depending on the operation mode. The variable resistance elements are configured to be accessible through multiple bit line combinations, allowing the same physical structure to support both conventional and spin-transfer torque writing methods without requiring additional manufacturing steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables the miniaturization of MRAM to a 6F2 cell size, simplifies manufacturing, reduces wiring resistance and parasitic capacitance, and enhances operational performance by allowing all bit lines to be formed at the same level, thereby improving the memory's efficiency and potential as a DRAM substitute.
Implementation Method 1
there have been developed MRAM, using so-called spin-transfer torque writing methods, which write data by directly applying a current to a magnetic tunnel junction (MTJ) element
Implementation Method 2
A magnetic random access memory (MRAM) is known as a resistance change memory which stores data by utilizing resistance switching of memory elements
Data Source
AI summary
A semiconductor memory device includes: a plurality of word lines extending in a first direction; first to third bit lines extending in a second direction that intersects with the first direction; a plurality of variable resistance elements each having a first terminal connected to either one of the first and third bit lines; a plurality of active areas extending in a direction oblique to the first direction while intersecting with the first to third bit lines; a plurality of select transistors provided on the active areas and each having a gate connected to a corresponding one of the word lines, and a current path whose one end is connected to a second terminal of a corresponding one of the variable resistance elements; and a plurality of contact plugs each connecting the other end of the current path of a corresponding one of the select transistors to the second bit line, wherein each of the active areas includes two select transistors sharing a diffusion region, the variable resistance elements includes a first variable resistance element group and a second variable resistance element group, the first variable resistance element group including variable resistance elements aligned in the second direction below the first bit line, and each disposed between adjacent two of the word lines, the second variable resistance element group including variable resistance elements aligned in the second direction below the third bit line, and each disposed between adjacent two of the word lines, and the contact plugs are aligned in the second direction below the second bit line, and are each disposed between adjacent two of the word lines.