MRAM Memory Cell Structure with Vertical MTJ and Groove Transistor
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Solution Overview
Problem
In MRAM memory cells, the high resistance of bit and word lines limits current control, and the presence of a data line increases the memory cell area, while heat treatment can degrade the Magnetic Tunnel Junction (MTJ) performance.
Innovation Solution
A memory cell structure with a transistor using a first diffusion layer in a groove-shaped concave portion of a silicon substrate and a second diffusion layer on the sidewalls, allowing for increased channel width and electrical insulation, and an MTJ element disposed below the first diffusion layer, connected via a contact after substrate thinning, which reduces wiring resistance and avoids heat-induced performance degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the bit line and word line are drawn to the MTJ in the mainstream structure, then the MTJ can be connected to the access transistor, but the resistance of the bit line and word line becomes large, limiting current control
Solution Approach 1:
The patent transitions from a planar wiring layout to a three-dimensional stacked architecture where the MTJ is positioned vertically above the access transistor. This dimensional change allows the bit line and word line to be routed through intermediate layers rather than drawn across the substrate surface, significantly reducing wiring resistance while maintaining electrical connectivity.
Solution Approach 2:
The patent introduces intermediate connection structures (contact holes and via layers) as mediators between the access transistor and MTJ. These intermediary elements provide low-resistance vertical pathways, replacing the high-resistance horizontal wire runs in conventional layouts and enabling effective current control.
2Ease of operation
If a data line is wired in the memory element, then the MTJ can be accessed, but the area of the memory element increases
Solution Approach 1:
The patent utilizes the vertical dimension to route the data line through stacked layers rather than expanding the planar footprint. The data line is connected to the MTJ through vertical vias and contact structures, allowing full data access functionality while maintaining a compact memory cell area comparable to conventional designs.
3Ease of manufacture
If heat treatment is performed in wiring of the word line, then the wiring can be formed, but performance degradation of the MTJ occurs
Solution Approach 1:
The patent performs preliminary actions by forming the MTJ structure and establishing its performance characteristics before conducting heat treatment processes for wiring formation. This sequence ensures that the MTJ is already in place and can be protected or annealed along with the wiring, preventing performance degradation that would occur if heat treatment were performed on already-formed sensitive MTJ structures.
Solution Approach 2:
The patent controls the timing and temperature parameters of heat treatment processes to be compatible with MTJ formation. By adjusting process parameters such as performing wiring heat treatment at temperatures and durations that do not degrade the MTJ, or by using low-temperature wiring formation techniques, the patent achieves both manufacturable wiring and preserved MTJ performance.
Data Source
AI summary
The present disclosure relates to a memory cell structure, a method of manufacturing a memory, and a memory apparatus that are capable of providing a memory cell structure of an MRAM, which reduces resistance of drawn wiring to be connected to an MTJ, reduces an area of a memory cell, and avoids performance degradation of the MTJ due to heat.A memory cell includes: a transistor that uses a first diffusion layer formed in a bottom portion of a concave portion formed by processing a silicon substrate into a groove shape, and a second diffusion layer formed in upper end portions of two opposing sidewall portions of the concave portion, to form channels at portions between the first diffusion layer and the second diffusion layer in the two sidewall portions; and a memory element that is disposed below the first diffusion layer. The first diffusion layer is electrically connected to the memory element via a contact formed after the silicon substrate is thinned.