MRAM Chip Segmentation for Speed-Density Trade-off
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Solution Overview
Problem
Conventional MRAM array layouts face a trade-off between high-speed memory access and high-density cell packing, with existing designs either offering fast speeds at the cost of low density or increased density at the expense of access speed, necessitating a new layout that balances both requirements.
Innovation Solution
An integrated circuit memory chip comprising a combination of high-speed and high-density magnetic memory cell arrays, where the high-speed array employs a ratio of switching devices to magnetoresistive stacks greater than one and the high-density array employs a ratio of one switching device per two or more stacks, with distinct logic and conductive lines for each array to optimize performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a one-to-one ratio of switches to MTJ stacks (1T1R) is used, then fast memory speeds are achieved, but array density is limited
Solution Approach 1:
The patent divides the memory array into multiple segments or blocks, where each block can be independently accessed. This segmentation allows the array to achieve high-speed access to individual blocks while maintaining high overall density through efficient packing of multiple blocks on the chip.
Solution Approach 2:
The patent transitions from a two-dimensional layout to a three-dimensional structure by stacking multiple layers of memory cells vertically. This vertical stacking enables high-density packing while maintaining fast access speeds through selective layer addressing, effectively adding a spatial dimension to resolve the contradiction.
2Speed
If a two-transistor design (2T1R) is used, then very fast speeds are provided, but cell density is insufficient due to large area occupied by switching devices
Solution Approach 1:
The patent merges multiple memory cells to share common switching devices and conductive lines. By combining several MTJ stacks under a single switch, the design reduces the total number of switching devices required, thereby decreasing the area occupied by control circuitry while maintaining fast access speeds through parallel operation capabilities.
Solution Approach 2:
The switching devices and conductive lines are designed to serve multiple functions and control multiple MTJ stacks simultaneously. This multi-functionality allows a single switch to manage several memory cells, reducing the overall component count and area requirements while preserving high-speed access characteristics.
3Quantity of substance
If one transistor is used for two or more MTJ stacks (1TnR), then increased MRAM cell density is achieved, but fast access speeds are lost
Solution Approach 1:
The patent implements dynamic control mechanisms where the switching devices can be selectively activated or deactivated based on access patterns. This dynamic operation allows the system to switch between high-density mode (where multiple stacks share a switch) and high-speed mode (where fewer stacks are actively accessed), optimizing performance for different operational requirements.
Solution Approach 2:
The patent employs periodic or pulsed activation of switching devices to access different groups of MTJ stacks in sequence. By organizing memory access into periodic cycles that target specific sub-arrays, the system maintains high density through shared switches while preserving fast access speeds by limiting active contention to small, manageable groups of cells at any given time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables a memory chip that simultaneously achieves high-speed and high-density memory cells, addressing the limitations of existing designs by providing fast access speeds and increased cell density on the same chip, suitable for diverse applications ranging from cache memory to data storage.
Implementation Method 1
The magnetization moment of the pinned ferromagnetic layer is pinned in a fixed direction. A very thin insulation layer forms the tunneling barrier between the pinned and free ferromagnetic layers. The MTJ memory device can be electrically represented as a resistor. The size of the resistance depends upon the orientation of the magnetization of the free ferromagnetic layer and the pinned ferromagnetic layer.
Implementation Method 2
An MTJ memory device comprises three basic layers, a free ferromagnetic layer, an insulating tunneling barrier, and a pinned ferromagnetic layer. The magnetization moments of the free ferromagnetic layer are free to rotate under an external magnetic field.
Implementation Method 3
To write or change the state in a basic MTJ memory device, an external magnetic field can be applied that is sufficient to completely switch the stable orientation of the magnetization of the free ferromagnetic layer.
Data Source
AI summary
Disclosed herein is a technique for created an advanced MRAM array for constructing a memory integrated circuit chip. More specifically, the disclosed principles provide for an integrated circuit memory chip comprised of a combination of at least one of an array of high-speed magnetic memory cells, and at least one of an array of high-density magnetic memory cells. Accordingly, a memory chip constructed as disclosed herein provides the benefit of both high-speed and high-density memory cells on the same memory chip. As a result, applications benefiting from the use of (or perhaps even needing) high-speed memory cells are provided by the memory cells in the high-speed memory cell array.