Comparison Buffer for MRAM Write Power Reduction
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Solution Overview
Problem
MRAM (magnetic RAM) experiences inefficiencies in data write operations due to wasteful power consumption and the inability to perform continuous writes when memory cells within the same bank are accessed repeatedly over a short time period, as data write operations require current flow through MTJ elements, leading to potential defective writes.
Innovation Solution
A semiconductor storage device with a comparison buffer that temporarily stores write data and reads data from selected memory cells, comparing logic states to only write data that differs from the existing data, thereby reducing power consumption and enabling continuous write operations by executing writes during the pre-charge period.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data write operations are performed by flowing current through MTJ elements, then data can be written to memory cells, but it takes significant time and causes power consumption issues when memory cells are repeatedly accessed
Solution Approach 1:
The patent applies preliminary action by reading the existing data from memory cells before performing the write operation. The read operation and data comparison are completed in advance during the active period, so that when the pre-charge period arrives, the decision to write or not write is already made, enabling faster write execution without compromising reliability
Solution Approach 2:
The patent segments the write operation into distinct phases: read phase (during active period), comparison phase (during active period), and write execution phase (during pre-charge period). This segmentation allows different operations to occur in parallel and optimizes the timing of current flow through MTJ elements, reducing overall write operation time while maintaining reliability
2Productivity
If data write operations are performed frequently on memory cells within the same bank, then continuous write capability is needed, but current flow through MTJ elements causes potential defective writes
Solution Approach 1:
The patent implements feedback by reading the current data state from memory cells and comparing it with the new data to be written. This feedback mechanism ensures that write operations are only performed when necessary (when data actually changes), preventing defective writes from repeated operations on the same cells and enabling reliable continuous write capability
Solution Approach 2:
The patent applies partial action by performing write operations only on memory cells where the new data differs from the existing data. Instead of writing to all selected cells unconditionally, the system selectively writes only to cells that need updating, improving productivity while maintaining reliability
3Speed
If write operations are performed unconditionally on selected memory cells, then write speed may be improved, but power is wastefully consumed when writing identical data
Solution Approach 1:
The patent uses feedback by comparing the read data with the new write data before executing the write operation. This comparison provides feedback on whether a write is actually needed, allowing the system to skip unnecessary write operations and save power while maintaining write speed for cells that do require updates
Solution Approach 2:
The patent applies partial action by performing write operations only on memory cells where data actually changes. Instead of unconditionally writing to all selected cells, the system selectively writes only to cells with different data values, reducing energy loss while maintaining effective write speed
4Loss of energy
If data comparison is performed between read data and write data, then power consumption is reduced by avoiding unnecessary writes, but additional circuit complexity is introduced
Solution Approach 1:
The patent applies universality by designing the comparison buffer to serve multiple functions: it temporarily stores read data, holds new write data, performs comparison operations, and generates control signals for selective writing. This multi-functionality reduces the need for separate dedicated circuits for each function, minimizing the increase in device complexity while achieving power savings through data comparison
Data Source
AI summary
A semiconductor storage device includes plural bit lines and plural word lines. The memory cell array has plural memory cells that are connected with the bit lines and word lines, and can store data. Plural sense amplifiers detect the data stored in the memory cells. Plural write drivers write data in the memory cells. A comparison buffer temporarily stores the write data to be written in the memory cells by the write driver. In a series of write sequences, the comparison buffer stores the read data from the memory cells selected as the write object and the write data to be written in the selected memory cells. After a series of write sequences, when the pre-charge command for resetting the voltage of the bit lines is received, the write execution command is executed so that the comparison buffer executes write in the selected memory cells.