MRAM Configuration Bit Circuitry for Secure FPGA Boot
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Solution Overview
Problem
Conventional configuration bit storage in FPGAs faces issues such as security concerns due to central storage, vulnerability to external radiation, slower boot times, and scalability limitations, especially with smaller scale technologies.
Innovation Solution
The use of magnetoresistive random-access memory (MRAM) or resistive random-access memory (ReRAM) as configuration bits within a small-scale integrated circuit, such as an FPGA, allows for secure, radiation-resistant, and scalable non-volatile memory solutions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If external non-volatile memory is used to store configuration bits, then security concerns arise due to centralized storage and vulnerability to external radiation, but this approach also requires significant peripheral analog circuitry and results in slower boot times
Solution Approach 1:
The patent extracts the configuration bit storage function from external non-volatile memory and relocates it directly into the FPGA fabric using non-volatile memory cells. This eliminates the need for peripheral analog circuitry for reading/writing configuration bits and removes the security vulnerabilities associated with external centralized storage.
Solution Approach 2:
The patent introduces non-volatile memory cells as an intermediary storage mechanism within the FPGA, replacing the traditional SRAM-based configuration storage. This intermediary solution provides both non-volatile persistence and direct integration, eliminating the need for external memory interfaces and analog circuitry while improving security and boot time.
2Loss of time
If external non-volatile memory is used for configuration bit storage, then boot time increases, but this approach also exposes configuration information to external radiation disruption
Solution Approach 1:
The patent segments the configuration storage into distributed non-volatile memory cells embedded throughout the FPGA fabric, rather than using a single external memory location. This segmentation provides both faster access (reducing boot time) and radiation hardness through spatial distribution, as radiation effects on individual cells do not compromise the entire configuration.
Solution Approach 2:
The patent implements local non-volatile memory storage at each configuration bit location within the FPGA, rather than centralized external storage. This local quality approach enables direct access during boot (reducing boot time) and provides inherent radiation hardening through distributed storage, where local failures do not affect global configuration.
3Duration of action of stationary object
If conventional non-volatile memory (Flash) is used in FPGA, then non-volatile storage is achieved, but a significant amount of additional circuitry is required which prevents scaling to smaller technologies
Solution Approach 1:
The patent merges the non-volatile memory storage function directly with the FPGA logic fabric by integrating non-volatile memory cells into the configurable logic blocks and routing resources. This consolidation eliminates the need for separate Flash memory blocks and associated control circuitry, enabling non-volatile functionality in scaled technologies where external or dedicated Flash memory would be impractical.
Solution Approach 2:
The patent creates a universal non-volatile memory cell structure that serves multiple functions: configuration bit storage, lookup table storage, and programmable logic state retention. This multi-functional approach eliminates the need for dedicated Flash memory circuits, allowing the same memory cells to provide non-volatile storage across different FPGA configurations and technology nodes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances security by decentralizing storage, reduces radiation vulnerability, speeds up boot times, and enables scalability to smaller manufacturing nodes, thereby addressing the limitations of conventional configuration bit storage.
Implementation Method 1
magnetoresistive random-access memory (MRAM)
Implementation Method 2
resistive random-access memory (Re RAM)
Data Source
AI summary
The present disclosure is drawn to, among other things, a configuration bit including at least four resistive elements and a voltage amplifier. At least two first resistive elements may be electrically connected in series via a first electrode and at least two second resistive elements may be electrically connected in series via a second electrode. The at least two first resistive elements may be electrically connected in parallel to the at least two second resistive elements via a third electrode and a fourth electrode. The first electrode and the second electrode may be electrically connected to a voltage supply. The third electrode and the fourth electrode may be electrically connected to an input of the voltage amplifier.