MRAM Cell with Dual Free Layers for Low-Current Switching
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Solution Overview
Problem
Existing MRAM memory cell designs face challenges in achieving high bit density and endurance due to high switching currents and low write margins, which limit the number of bits that can be fabricated per chip area and reduce memory cell reliability.
Innovation Solution
The proposed MRAM memory cell design incorporates a second free layer with a higher temperature dependence of coercivity than the first free layer, utilizing self-heating to change the magnetization axis from perpendicular to in-plane, allowing for lower write currents and increased write margins through spin transfer torque and dipolar stray magnetic fields, thereby enhancing bit density and endurance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional MRAM memory cell designs are used, then magnetization switching can be achieved, but high switching currents are required which limit bit density and endurance
Solution Approach 1:
The patent changes the temperature parameter by utilizing self-heating effects during write operations. The localized heating temporarily reduces the coercivity of the free layer, enabling magnetization switching at lower currents. This parameter change resolves the contradiction by allowing reliable switching (improved endurance) while reducing the energy required (lower switching current).
Solution Approach 2:
The patent exploits the phase transition-like behavior of magnetic anisotropy with temperature. By heating the free layer above its compensation temperature, the magnetization direction transitions from perpendicular to in-plane, fundamentally changing the switching mechanism and enabling low-current operation that improves both endurance and reduces energy consumption.
2Reliability
If high switching currents are used to achieve magnetization switching, then reliable write operations can be performed, but the write margin is reduced which limits memory cell reliability
Solution Approach 1:
The patent changes the temperature parameter during write operations through self-heating, which dynamically modifies the coercivity and anisotropy of the free layer. This parameter change creates a larger window between the write current threshold and breakdown voltage, improving write margin while reducing the actual write current required, thus resolving the contradiction between reliability and energy use.
3Productivity
If conventional single free layer designs are used, then结构简单 (structure is simple), but high write currents are required which reduce bit density
Solution Approach 1:
The patent segments the magnetic memory cell into distinct functional layers including a pinned layer, tunnel barrier, and free layer with specific perpendicular magnetic anisotropy. This segmentation allows each layer to be optimized independently, with the free layer designed to exhibit temperature-dependent coercivity that enables low-current switching, thereby increasing bit density while reducing write current requirements.
Solution Approach 2:
The patent employs composite material structures, specifically a pinned layer comprising alternating ferromagnetic and non-magnetic layers, and a free layer with tailored composition exhibiting perpendicular magnetic anisotropy. These composite structures enable the temperature-dependent magnetic properties necessary for low-current switching, resolving the contradiction between high bit density and low write current by achieving both through material design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves lower switching currents, higher bit density, and improved memory cell endurance by reducing the write current and increasing the write margin, enabling more efficient and reliable memory operations.
Implementation Method 1
The cap layer and the tunnel barrier are configured to generate heat in response to a current through the cap layer and the tunnel barrier
Implementation Method 2
The first free layer is configured to switch its direction of magnetization between parallel and anti-parallel to the direction of magnetization of the pinned layer in response to spin transfer torque
Implementation Method 3
low resistance typically represents a '0' bit and high resistance typically represents a '1' bit
Data Source
AI summary
A magnetoresistive random access memory (MRAM) memory cell comprises a pinned layer having fixed direction of magnetization that is perpendicular to a plane of the pinned layer, a first free layer having a direction of magnetization that can be switched and is perpendicular to a plane of the first free layer, a tunnel barrier positioned between the pinned layer and the first free layer, a second free layer having a direction of magnetization that can be switched, and a spacer layer positioned between the first free layer and the second free layer. Temperature dependence of coercivity of the second free layer is greater than temperature dependence of coercivity of the first free layer.