MRAM Gate Structure with Dummy Gate for Leakage Control
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Solution Overview
Problem
Current magnetoresistive random access memory (MRAM) devices face issues such as high chip area, high cost, high power consumption, and sensitivity to temperature variations, which affect their performance and reliability.
Innovation Solution
The method involves forming a semiconductor device with a dummy gate and control gates on a substrate, where a doped region is created under the dummy gate to have a higher threshold voltage than the control gates, and adjusting the work function to achieve optimal performance, along with the formation of magnetic tunneling junctions for improved functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional MRAM devices are fabricated without optimized gate structures, then the device structure is simpler, but leakage current increases and threshold voltage control deteriorates
Solution Approach 1:
The gate structure is segmented into multiple components: a first control gate, a second control gate, and a dummy gate. Each gate has independent threshold voltage control through separate doped regions, allowing independent optimization of leakage control and switching performance without increasing overall device complexity
Solution Approach 2:
Different doped regions are created under each gate structure with specific conductivity types and doping concentrations. The first doped region under the first control gate has different properties than the second doped region under the second control gate, enabling localized optimization of threshold voltages to minimize leakage current while maintaining performance
2Reliability
If magnetic field sensor technologies such as AMR sensors, GMR sensors, and MTJ sensors are used, then sensing functionality is achieved, but chip area increases and cost increases
Solution Approach 1:
The gate control structure is designed to serve multiple functions: it controls the threshold voltage of the underlying transistor, enables magnetic field sensing through the magnetic tunneling junction, and provides leakage current control. This multi-functionality eliminates the need for separate dedicated sensing structures, reducing chip area while maintaining sensing capability
Solution Approach 2:
The control gate structure is merged with the magnetic tunneling junction stack, where the gates directly control the switching behavior of the MTJ. This integration combines the advantages of CMOS control with magnetic field sensing in a single compact structure, reducing both chip area and manufacturing cost
3Use of energy by moving object
If conventional gate structures are used without work function adjustment, then manufacturing is simpler, but power consumption increases and temperature stability deteriorates
Solution Approach 1:
The work function of the control gates is adjusted by modifying the doping concentration and conductivity type of the doped regions underneath. By changing these parameters, the threshold voltage of each gate can be precisely controlled to optimize power consumption and temperature stability without requiring complex additional manufacturing steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces leakage and enhances the performance of MRAM devices by optimizing threshold voltages and work functions, leading to improved sensitivity, reduced power consumption, and increased robustness against temperature variations.
Implementation Method 1
performing a treatment process so that a threshold voltage of the dummy gate is greater than a threshold voltage of the first control gate
Implementation Method 2
the characterization of utilizing GMR materials to generate different resistance under different magnetized states
Data Source
AI summary
A semiconductor device includes: a dummy gate on a substrate; a first control gate on one side of the dummy gate and a second control gate on another side of the dummy gate; a well in the substrate, wherein the well comprises a first conductive type; a first source/drain region between the dummy gate and the first control gate, wherein the first source/drain region comprises a second conductive type; a second source/drain region between the dummy gate and the second control gate, wherein the second source/drain region comprises the second conductive type; and a doped region directly under the dummy gate, wherein the doped region comprises the first conductive type.