MRAM Bit Line Layout Using Dummy MTJ Elements
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional MRAMs face challenges in downscaling and achieving high integration and mass storage capacity due to non-uniform arrangement of MTJ elements on semiconductor substrates, which complicates lithographic and etching processes and requires additional processing steps for dummy elements.
Innovation Solution
The proposed semiconductor storage device arranges MTJ elements and cell transistors alternately in series between bit lines, with staggered layouts to facilitate uniform placement and reduce the pitch between adjacent elements, allowing for more efficient lithographic and etching processes and increased storage capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If MTJ elements are arranged non-uniformly on semiconductor substrate, then storage capacity is increased, but lithographic and etching processing becomes more difficult
Solution Approach 1:
The patent introduces dummy MTJ elements in specific locations (spaces between adjacent MTJ elements) to create a uniform appearance for processing purposes, while maintaining the actual non-uniform arrangement for high storage capacity. This allows different regions of the substrate to have different functions: real MTJ elements provide storage capacity, while dummy elements provide processing uniformity.
2Stability of the object's composition
If dummy MTJ elements are added to uniformize arrangement, then processing stability is improved, but device complexity and processing steps increase
Solution Approach 1:
The patent extracts the function of uniform arrangement from the actual MTJ elements by introducing separate dummy MTJ elements. This allows the real MTJ elements to focus on storage capacity while the dummy elements handle the uniform arrangement requirement, separating the two functions to reduce overall complexity.
3Area of moving object
If MTJ element area is reduced for downscaling, then integration density is improved, but reversal threshold current control becomes more difficult
Solution Approach 1:
The patent changes the physical parameters of the MTJ elements by introducing dummy elements with different characteristics (no magnetic tunnel junction structure, different material composition) to compensate for the reduced size of real MTJ elements. This allows the real MTJ elements to be smaller while maintaining controlled reversal threshold currents through the modified overall structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables downscaled MRAMs with improved storage capacity and reduced chip size, simplifying the connection arrangement between sense amplifiers and bit lines, and reducing the number of sense amplifiers needed, thus enhancing read margins and operational efficiency.
Implementation Method 1
magnetic field writing and spin-transfer torque writing are normally known as data writing techniques and these techniques are advantageous in high speed processing because of the use of the magnetization reversal of magnetic bodies
Implementation Method 2
The spin-transfer torque writing has a characteristic such that a spin injection current becomes smaller in an amount necessary for magnetization reversal as magnetic bodies is smaller in size
Data Source
AI summary
A semiconductor storage device according to the present embodiment includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells each including a storage element and a switching element which are connected in series between adjacently paired ones of the bit lines. Gates of the switching elements of the memory cells connected between one of the adjacently paired ones of the bit lines are respectively connected to different ones of the word lines. A plurality of the storage elements and a plurality of the switching elements of the adjacent memory cells are alternately connected in series.