MRAM Dummy Via Layout for Uniform Edge Cell Patterning
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Solution Overview
Problem
In the magnetoresistive random access memory (MRAM) process, the optical effects during patterning can result in smaller dimensions of memory cells at the edge of the memory region, affecting device performance, and the use of dummy regions and non-conductive vias can lead to smaller via apertures, increasing resistance and reducing tunneling magnetoresistance.
Innovation Solution
The implementation of dummy vias around the memory region during the manufacturing process of non-volatile memory devices, where the dummy vias are not electrically connected and have a smaller aperture than conductive vias, prevents the optical effect from affecting the profile of conductive vias and memory cells, ensuring consistent dimensions and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If dummy regions with dummy memory cells are disposed around the memory region to prevent optical effect from affecting memory cell dimensions, then memory cell dimension consistency is improved, but the aperture of conductive vias at the edge becomes smaller and resistance increases
Solution Approach 1:
The patent segments the dummy structures into two distinct types: dummy memory cells (non-conductive) disposed around the memory region to protect against optical effects, and separate dummy vias (conductive) disposed around conductive vias to maintain via aperture. This segmentation allows each component to fulfill its specific function without compromising the other.
Solution Approach 2:
The dummy vias act as intermediary structures that mediate between the optical effect protection requirement and the conductive via aperture requirement. By placing dummy vias around the conductive vias, they serve as a buffer that prevents the optical effect from directly affecting the conductive via dimensions, thereby maintaining via aperture and resistance characteristics.
2Reliability
If no conductive vias are disposed under dummy memory cells to prevent electrical connection issues, then device performance is maintained, but the aperture of edge conductive vias becomes smaller due to optical effect
Solution Approach 1:
The patent segments the dummy structures into two distinct types: dummy memory cells (non-conductive) disposed around the memory region to protect against optical effects, and separate dummy vias (conductive) disposed around conductive vias to maintain via aperture. This segmentation allows each component to fulfill its specific function without compromising the other.
Solution Approach 2:
The dummy vias act as intermediary structures that mediate between the optical effect protection requirement and the conductive via aperture requirement. By placing dummy vias around the conductive vias, they serve as a buffer that prevents the optical effect from directly affecting the conductive via dimensions, thereby maintaining via aperture and resistance characteristics.
3Manufacturing precision
If dummy vias are disposed around the memory region to protect conductive vias from optical effect, then conductive via aperture consistency is improved, but device complexity increases
Solution Approach 1:
The dummy vias structure serves multiple functions: it protects conductive vias from optical effects during patterning, maintains via aperture consistency, and can be integrated into the existing dummy region layout. By designing the dummy vias to align with the circular arrangement of dummy memory cells, the structure achieves multi-functionality without proportionally increasing complexity.
Data Source
AI summary
Provided are a non-volatile memory device and a manufacturing method thereof. The non-volatile memory device includes a substrate having a memory region and a dummy region surrounding the memory region, an interconnect structure, memory cells, conductive vias and dummy vias. The interconnect structure is disposed on the substrate and in the memory region. The memory cells are disposed on the interconnect structure and arranged in an array when viewed from a top view. The memory cells include first memory cells in the memory region and second memory cells in the dummy region. The conductive vias are disposed in the memory region and between the first memory cells and the interconnection structure to electrically connect each of the first memory cells to the interconnect structure. The dummy vias are disposed in the dummy region and surround the memory region.