Hierarchical MRAM ECC Architecture for Low-Area Error Correction
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Solution Overview
Problem
Existing memory devices, such as MRAM, face challenges in efficiently protecting data integrity due to bit corruption caused by environmental and internal factors, which requires effective error correction mechanisms without excessive area and power consumption.
Innovation Solution
A hierarchical ECC structure is implemented, where local ECC circuits in each MRAM macro detect errors and share a global ECC circuit for error correction, balancing area requirements and power consumption by minimizing unnecessary data communication and circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a global ECC circuit is used for all memory macros, then error correction capability is provided, but area overhead and power consumption increase
Solution Approach 1:
The ECC functionality is segmented into two distinct parts: local ECC circuits embedded within each memory macro for error detection, and a separate global ECC circuit for error correction. This segmentation allows the detection function to be distributed close to data sources while the correction function is centralized, reducing the area overhead compared to providing full ECC capability in every macro.
Solution Approach 2:
The error correction functionality is extracted from the local memory macros and placed in a dedicated global ECC circuit. Only the error detection function remains in the local ECC circuits. This extraction allows the correction logic to be shared across all macros, significantly reducing the total area required while maintaining full error correction capability.
2Reliability
If local ECC circuits are added to each memory macro, then error detection capability is improved, but area overhead increases
Solution Approach 1:
The local ECC circuits are designed with a specialized quality optimized for error detection only, using simplified logic tailored to this specific function. This local optimization allows efficient detection capability in each macro without including the more complex correction logic, thereby minimizing area overhead while maximizing detection effectiveness at the local level.
3Reliability
If full ECC capability is provided in each memory macro, then error correction is available locally, but power consumption and area increase
Solution Approach 1:
The error correction operations for all memory macros are merged into a single global ECC circuit. Instead of having separate correction circuits in each macro that would all be active simultaneously, the global circuit processes corrections for multiple macros in sequence, sharing the correction logic and reducing total power consumption while maintaining local correction capability when needed.
4Area of stationary object
If a hierarchical ECC structure is implemented, then area and power are reduced, but data communication between local and global ECC circuits is required
Solution Approach 1:
The local ECC circuits act as intermediaries between the memory macros and the global ECC circuit. They perform initial error detection and filter out cases where no errors are present, only forwarding error syndromes to the global circuit when needed. This intermediary role simplifies the communication structure by reducing the volume of data that needs to be transmitted to the global circuit.
Data Source
AI summary
A memory device, such as a MRAM device, includes a plurality of memory macros, where each includes an array of memory cells and a first ECC circuit configured to detect data errors in the respective memory macro. A second ECC circuit that is remote from the plurality of memory macros is communicatively coupled to each of the plurality of memory macros. The second ECC circuit is configured to receive the detected data errors from the first ECC circuits of the plurality of memory macros and correct the data errors.