MRAM ECC Inversion Scheme for Low-Energy Reliable Writes
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Solution Overview
Problem
Magnetic random access memories (MRAMs) experience higher energy consumption and error rates compared to non-magnetic memory devices like DRAMs, particularly during data reading and writing, and existing error correction mechanisms are inadequate for inverted bits used in energy-saving schemes.
Innovation Solution
Implementing a majority detection and inversion scheme in MRAMs, where bits are inverted only when a majority are ones, reducing energy consumption by writing fewer bits, and incorporating inversion bits within error correction codes (ECC) to enhance error correction, along with generating parity bits that match both original and inverted states to ensure accurate encoding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If bits are inverted to reduce energy consumption during writing, then energy consumption decreases, but error rates increase
Solution Approach 1:
The patent performs majority detection and inversion decisions before the write operation. The system determines in advance whether inversion is needed based on the current bit states, then applies inversion only when beneficial. This preliminary action allows energy optimization to be planned and executed systematically, reducing unnecessary bit switching while maintaining data integrity through pre-calculated inversion strategies.
Solution Approach 2:
The patent implements feedback mechanisms where the system monitors bit states, detects majority conditions, and adjusts inversion decisions based on current memory array states. The error correction codes provide feedback about data integrity, allowing the system to compensate for inversion-related errors. This closed-loop feedback ensures that energy-saving inversions do not compromise overall system reliability.
2Reliability
If robust error correction codes are implemented to reduce error rates, then reliability improves, but energy consumption increases
Solution Approach 1:
The patent applies error correction selectively rather than uniformly to all data operations. By implementing majority detection and inversion only when beneficial, the system avoids the full energy cost of robust error correction in every operation. The error correction capability is enhanced precisely where needed (inverted bits) while maintaining energy efficiency in normal operations, achieving partial application of error correction strategies.
Solution Approach 2:
The patent changes the state parameters of bits through inversion, transforming them from original states to inverted states. This parameter change allows the system to reduce the number of bits that need error correction processing, as inverted bits have predictable patterns. By changing bit states strategically, the system reduces the computational burden and energy consumption of error correction operations while maintaining reliability.
3Use of energy by moving object
If majority detection and inversion scheme is implemented to reduce bit switching, then energy consumption decreases, but device complexity increases
Solution Approach 1:
The patent segments the error correction process by separating majority detection, inversion decision-making, and actual inversion operations. This segmentation allows each function to be handled by dedicated circuitry or software routines, making the complex inversion scheme more manageable and implementable. The segmentation also enables parallel processing of different aspects of the inversion strategy, reducing overall complexity despite the enhanced functionality.
Solution Approach 2:
The patent implements a universal inversion mechanism that can be applied across different memory operations and data patterns. The majority detection and inversion logic serves multiple functions: reducing energy consumption, maintaining data integrity, and working with various error correction codes. This multi-functionality justifies the added device complexity by providing broad benefits across different operational contexts.
Data Source
AI summary
In some examples, a memory device may be configured to store data in either an original or an inverted state based at least in part on whether the majority of bits are set to a high state or a low state. For instance, the memory device may be configured to set each bit in the memory array to a low state when the data is read. The memory device may then be configured to store the data in the original state when a majority of the bits to be written to the array are in the low state and in the inverted state when the majority of the bits to be written to the array are in the high state.