MRAM ECC Word Layout for Dual-Level Error Correction
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Solution Overview
Problem
Memory devices, particularly magnetic random access memories (MRAMs), experience higher inherent random errors during access operations compared to dynamic random access memories (DRAMs), leading to inefficiencies in error correction and system-level error correction challenges.
Innovation Solution
Implementing a memory device with dual levels of error correction - a first level within the memory device and a second level at the system level, where the first level corrects bit errors per ECC word and the second level corrects errors across multiple ECC words, with data output configured to reduce additional errors passing to the system level, and using time multiplexing and interleaving to improve processing speed and error correction efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single level of error correction is implemented in the memory device, then the device complexity is reduced, but the reliability is insufficient due to higher error rates in MRAM compared to DRAM
Solution Approach 1:
The error correction function is segmented into two independent levels: device-level ECC circuitry within the memory device and system-level ECC circuitry in the external device. Each level operates independently on different portions of data, with the device-level correcting errors in first portions and the system-level correcting errors in second portions. This segmentation allows each correction level to be simpler while collectively providing robust error correction for MRAM's higher error rates.
2Productivity
If data is output from multiple I/O pads per ECC word, then the processing speed is improved, but the reliability deteriorates due to increased likelihood of multiple errors passing to system-level correction
Solution Approach 1:
The data output is segmented such that each I/O pad outputs data from different ECC words during the same access operation. This segmentation ensures that if multiple errors occur, they are distributed across different ECC words and can be handled by the device-level correction circuitry for each ECC word independently, preventing multiple errors from the same ECC word from overwhelming the system-level correction.
Solution Approach 2:
The device-level ECC circuitry provides feedback correction by detecting and correcting errors in each ECC word before data is output through I/O pads. This feedback mechanism ensures that only corrected or single-error ECC words are output, reducing the burden on system-level correction and maintaining reliability even with high-speed multi-pad output.
3Reliability
If dual levels of error correction are implemented with orthogonal configuration, then the reliability is improved, but the device complexity increases
Solution Approach 1:
The dual-level correction system is segmented with clear functional boundaries: device-level ECC circuitry handles first portions of data from specific ECC words, while system-level ECC circuitry handles second portions from different ECC words. This segmentation prevents the need for complex interaction between correction levels, as each operates independently on its designated data portions.
Solution Approach 2:
The device-level ECC circuitry is designed to be universal by providing correction capability for multiple ECC words through a single access operation. The circuitry can handle correction for any ECC word that outputs data through the I/O pads, making the correction mechanism adaptable to different data access patterns without requiring dedicated correction circuits for each ECC word.
4Device complexity
If time multiplexing is used for data output, then the device complexity is reduced, but the processing speed deteriorates
Solution Approach 1:
Time multiplexing implements periodic action by cycling through different ECC words assigned to each I/O pad in a systematic sequence. During a single access operation, each I/O pad sequentially outputs data from its assigned ECC words over multiple cycles. This periodic pattern allows efficient utilization of limited I/O pads while maintaining high throughput through parallel processing of multiple ECC words.
Data Source
AI summary
A memory device includes memory arrays configured to store pages of data organized into multiple ECC words. The memory device also includes at least one input/output pad for each ECC word associated with a page, such that a first level of error correction is performed by the memory device on each of the ECC words associated with a page, and a second level of error correction is performed on the data output by each of the input/output pads, during a particular period of time. Each of the one or more input/output pads of the memory device is configured to provide only one bit of data per ECC word to an external source during an access from the external source.