MRAM Interconnect Layout With Etch Stop Protection for MTJ Landing

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Solution Overview

Problem

The challenge of forming a reliable electrical connection between the top electrode and the interconnect wire in magnetic tunnel junction (MTJ) devices, such as MRAM, is exacerbated by the difficulty in landing the interconnect wire accurately due to over-etching, which can damage the MTJ and reduce yield.

Innovation Solution

Incorporating an etch stop layer over the MTJ device to protect it during fabrication, allowing for separate processes to expose and remove the etch stop layer, thereby forming an upper interconnect wire without significant damage to the MTJ, thus improving the process window and reducing fabrication costs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional fabrication processes are used to form interconnect wires, then manufacturing simplicity is maintained, but over-etching damages the MTJ device and reduces yield

Engineering Contradiction:
ImproveMTJ device integrityVSAvoidfabrication yield
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

An etch stop layer is formed over the MTJ device before subsequent fabrication steps. This layer serves as a protective barrier during etching operations, preventing over-etching from damaging the MTJ while still allowing the interconnect wire to be formed. The preliminary placement of this protective layer resolves the contradiction by enabling both reliable MTJ protection and successful interconnect formation.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The etch stop layer acts as an intermediary element between the MTJ device and the etching process. It mediates the interaction by absorbing the harmful effect of over-etching, thereby protecting the MTJ while still permitting the etch process to proceed and form the interconnect wire structure.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If the etch stop layer is removed to form the interconnect wire, then good electrical connection is achieved, but additional process steps increase fabrication complexity

Engineering Contradiction:
Improveelectrical connection qualityVSAvoidnumber of process steps
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The removal of the etch stop layer is merged with the formation of the interconnect wire trench in a single integrated process step. Rather than separately removing the etch stop layer and then forming the trench, the etching process accomplishes both tasks simultaneously, thereby achieving good electrical connection while minimizing additional process complexity.

Inventive Principle:
Principle #5Merging (Combining)

3Manufacturing precision

If photomasks are used to define the interconnect wire pattern, then manufacturing precision is improved, but the number of photomasks increases production cost

Engineering Contradiction:
Improveinterconnect wire placement accuracyVSAvoidfabrication cost
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The etch stop layer serves multiple functions: it protects the MTJ during etching, defines the interconnect wire pattern, and eliminates the need for separate photomask alignment steps. By making the etch stop layer multi-functional, the patent achieves precise interconnect wire placement while reducing the total number of photomasks required, thereby lowering fabrication costs.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20250316537A1Semiconductor memory device and method of formation
Publication Date: 2025.10.09 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250316537A1 patent drawing
  • US20250316537A1 patent drawing
  • US20250316537A1 patent drawing

AI summary

The present disclosure relates to an integrated chip in some embodiments. The integrated chip includes a memory device having a switching layer arranged between a lower electrode and an upper electrode. An inter-level dielectric (ILD) laterally surrounds the memory device. An upper interconnect is arranged directly over and along one or more sides of the memory device. A bottom of the upper interconnect is vertically below a bottom of the upper electrode.