MRAM Etching Using Annular Spacer Masks for High Density
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Solution Overview
Problem
Conventional DRAM devices face limitations in scaling down while maintaining capacitance, prompting the development of alternative semiconductor memory structures like MRAM, which utilizes Tunneling Magneto-Resistance (TMR) in magnetic tunnel junctions (MTJs) for data storage, but requires efficient manufacturing methods to enhance integration and operation speed.
Innovation Solution
A method for manufacturing MRAM devices involving the formation of magnetic tunnel junction layers, spacers, and upper electrodes, with etching processes using specific etch masks to create concentrically aligned MTJs, allowing for improved data storage and integration by optimizing the structure and connectivity of MTJs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional DRAM scaling is pursued, then device density increases, but capacitance maintenance becomes difficult
Solution Approach 1:
The patent transitions from charge-based storage (DRAM) to magnetoresistance-based storage (MRAM), fundamentally changing the physical parameter used for data storage. This allows scaling to higher densities while maintaining data retention capabilities through TMR effect in magnetic tunnel junctions rather than relying on capacitor integrity at scaled dimensions
2Reliability
If MTJ structure is used for MRAM, then non-volatile storage is achieved, but manufacturing complexity increases
Solution Approach 1:
The patent employs concentric circular patterns where spacers are formed around magnetic tunnel junction layers, which are themselves surrounded by electrode structures. This nested circular geometry enables multi-bit storage within a single cell while maintaining systematic fabrication processes that build upon each other in defined sequences
Solution Approach 2:
The memory cell is divided into distinct functional segments: magnetic tunnel junction layers for data storage, spacer structures for geometric definition, upper electrodes for electrical connection, and lower electrodes for current injection. This segmentation allows independent optimization and systematic manufacturing of each component
3Productivity
If multi-bit storage per cell is implemented, then integration density improves, but etching precision requirements increase
Solution Approach 1:
The patent uses circular spacer patterns and concentric ring structures instead of conventional rectangular geometries. This circular geometry provides more uniform etching profiles, reduces corner-related defects, and enables better control over pattern dimensions during the etching process, thereby achieving the required precision for multi-bit cell formation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the storage of multi-bit data in a single unit cell, enhancing the integration and operation speed of non-volatile MRAM devices by leveraging the TMR effect in magnetic tunnel junctions.
Implementation Method 1
a Magneto-resistive Random Access Memory (MRAM) device uses the characteristics of Tunneling Magneto-Resistance (TMR). The TMR is a magneto-resistive effect that occurs in a magnetic tunnel junction (MTJ).
Implementation Method 2
The STT technique uses spin-aligned ('polarized') electrons to directly torque domains. The torque will be transferred to a nearby ferromagnetic plate, according to an effect that may modify the orientation of a ferromagnetic plate in a tunnel magnetoresistance or spin valve using a spin-polarized current.
Data Source
AI summary
A method for manufacturing a semiconductor memory device includes forming a magnetic tunnel junction layer on a lower electrode, forming a spacer having an annular shape on the magnetic tunnel junction layer, forming upper electrodes on both sidewall surfaces of the annular shaped spacer, removing the spacer, and etching the magnetic tunnel junction layer by using the upper electrodes as an etch mask.