MRAM Emulation via FIFO Write Buffering
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Solution Overview
Problem
Magnetic random access memory (MRAM) devices face limitations in write access time, which is slower than static random access memory (SRAM), making them less suitable for applications requiring fast data storage and retrieval, despite their non-volatile nature and smaller size.
Innovation Solution
A magnetic memory system incorporating magnetic tunnel junctions (MTJs) and a first-in-first-out (FIFO) interface device that queues write commands and performs concurrent write operations across multiple magnetic memory banks, allowing for faster write operations by issuing queued commands when the MRAM is not in use, thus emulating SRAM performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If MRAM is used for data storage, then non-volatility and smaller size are achieved, but write access time becomes slower compared to SRAM
Solution Approach 1:
The patent implements a write buffer that temporarily stores write data before it is transferred to the MRAM array. This preliminary action allows the system to accept write commands at SRAM speeds while the actual write operation to the non-volatile MRAM cells occurs asynchronously in the background, thus resolving the contradiction between fast write access and non-volatility.
Solution Approach 2:
The patent introduces a write buffer as an intermediary component between the CPU and the MRAM array. This buffer acts as a mediator that decouples the fast write operations from the slower non-volatile storage operations, allowing the CPU to write data quickly while the MRAM performs its slower but persistent storage in the background.
2Productivity
If burst operations are used to compensate for slower write access time, then more data units can be written, but data must be sequential and large burst sizes are not practical
Solution Approach 1:
The write buffer pre-stores incoming write data in a structured format, organizing it into fixed-size bursts before transfer to the MRAM array. This preliminary organization allows the system to efficiently handle sequential data bursts while the buffer manages the complexity of data reorganization, making the sequential requirement transparent to the CPU.
Solution Approach 2:
The patent transforms the write operation from a direct CPU-to-MRAM sequence into a two-dimensional process: first writing to the buffer (fast, random access), then transferring to the MRAM array in optimized bursts (slower, sequential). This dimensional separation allows the system to accept random write commands from the CPU while optimizing the actual memory writes as sequential bursts.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The system achieves write operation performance comparable to SRAM by utilizing a FIFO interface to manage and synchronize write commands, enhancing the overall system performance and reducing the need for sequential data, thereby overcoming the slower write access time of MRAM.
Implementation Method 1
magnetic random access memory (MRAM) including a plurality of magnetic memory banks
Implementation Method 2
magnetic memory system comprises a magnetic random access memory (MRAM) including a plurality of magnetic memory banks
Data Source
AI summary
A magnetic memory system includes a magnetic random access memory (MRAM) including a plurality of magnetic memory banks and operative to store data during a write operation initiated by a write command. The magnetic memory system further includes a first-in-first-out (FIFO) interface device coupled to the MRAM and including a plurality of FIFOs Each of the magnetic memory banks is coupled to a respective one of the plurality of FIFOs, the FIFO being operative to queue write commands on a per magnetic memory bank basis and further operative to issue the queued write commands at a time when the MRAM is not in use, wherein concurrent write operations are performed to at least two of the plurality of magnetic memory banks.