Embedded MRAM Configuration Bit for Secure FPGA Boot
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Solution Overview
Problem
Conventional FPGA configuration bit implementations face issues with security, scalability, and performance due to the use of external non-volatile memory, which can be disrupted by radiation and require significant peripheral circuitry, making them unsuitable for smaller scale technologies.
Innovation Solution
Implementing magnetoresistive random-access memory (MRAM) or resistive random-access memory (ReRAM) as configuration bits within the FPGA, allowing for multi-time or one-time programmability without external communication, reducing the need for peripheral circuitry and enhancing security.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If external non-volatile memory is used to store configuration bits, then non-volatile storage is achieved, but security is compromised and device complexity increases due to peripheral circuitry requirements
Solution Approach 1:
The patent extracts the non-volatile storage function from external memory and relocates it directly into the FPGA fabric using embedded MRAM/ReRAM cells. This eliminates the external memory interface and associated peripheral circuitry, thereby improving security by removing external access points while maintaining non-volatile configuration storage within the device boundaries.
Solution Approach 2:
The patent merges the configuration storage function with the FPGA logic fabric by integrating MRAM/ReRAM cells directly into the configurable logic blocks and routing structures. This consolidation eliminates separate external memory components and their associated control circuitry, reducing device complexity while achieving secure internal non-volatile storage.
2Duration of action of stationary object
If external non-volatile memory is used for configuration storage, then non-volatile storage is achieved, but device complexity increases due to peripheral analog circuitry requirements
Solution Approach 1:
The patent removes the external memory interface and associated peripheral analog circuitry by extracting the non-volatile storage function and relocating it to embedded MRAM/ReRAM cells within the FPGA. This eliminates complex external memory controllers, data buses, and analog-to-digital converters that would otherwise be required.
Solution Approach 2:
The patent combines the configuration storage function with the digital logic fabric using embedded MRAM/ReRAM cells that can be directly controlled by digital circuits. This merger eliminates the need for separate peripheral analog circuitry for reading and writing configuration data, as the memory operations can be performed directly through digital interfaces within the FPGA.
3Duration of action of stationary object
If conventional non-volatile memory (Flash) is used in FPGA, then non-volatile storage is achieved, but scalability is limited due to additional circuitry requirements
Solution Approach 1:
The patent changes the fundamental technology parameter from conventional Flash memory to emerging MRAM/ReRAM technologies, which have different physical characteristics and circuit requirements. This parameter change enables scalability to smaller fabrication nodes (below 28nm) while maintaining non-volatile storage functionality, as MRAM/ReRAM cells can be implemented with smaller feature sizes and fewer process steps.
Solution Approach 2:
The patent replaces the mechanical/physical structure of conventional Flash memory cells with MRAM/ReRAM cell structures that are better suited for small-scale integration. This substitution allows for denser packing of memory cells within the FPGA fabric, enabling scalability to advanced technology nodes without the circuitry constraints that limit Flash memory implementation.
4Duration of action of stationary object
If external memory is used for configuration storage, then non-volatile storage is achieved, but boot time increases due to slower access speed
Solution Approach 1:
The patent extracts the configuration storage from external memory and places it directly within the FPGA device using embedded MRAM/ReRAM cells. This relocation eliminates the external memory access bottleneck, allowing configuration data to be loaded directly from internal non-volatile storage without the delays associated with external memory interfaces and data buses.
Solution Approach 2:
The patent merges the configuration storage with the FPGA logic fabric, allowing configuration data to be directly accessed by the configurable logic blocks without external memory access. This integration enables faster configuration loading during boot-up, as the MRAM/ReRAM cells can be read directly into the logic elements through internal routing rather than through external memory controllers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves security and reduces circuitry complexity, enabling scalability to smaller manufacturing scales by eliminating the need for external memory and simplifying boot time, while maintaining data integrity.
Implementation Method 1
magnetoresistive random-access memory (MRAM) or resistive random-access memory (ReRAM)
Data Source
AI summary
The present disclosure is drawn to, among other things, a configuration bit including at least four resistive elements and a voltage amplifier. At least two first resistive elements may be electrically connected in series via a first electrode and at least two second resistive elements may be electrically connected in series via a second electrode. The at least two first resistive elements may be electrically connected in parallel to the at least two second resistive elements via a third electrode and a fourth electrode. The first electrode and the second electrode may be electrically connected to a voltage supply. The third electrode and the fourth electrode may be electrically connected to an input of the voltage amplifier.