Hierarchical MRAM ECC for Low-Area Error Correction
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Solution Overview
Problem
Existing memory technologies face challenges in efficiently balancing area requirements and power consumption for error correction, particularly in MRAM devices, due to the need for both local and shared ECC circuitry, which increases energy consumption and latency.
Innovation Solution
Implementing a hierarchical ECC structure with local error detection circuits in each MRAM macro and a shared global error correction circuit, reducing area overhead and global data communication energy by only transmitting detected errors for correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If local ECC circuits are implemented in each MRAM macro, then error detection capability is improved, but area overhead and power consumption increase
Solution Approach 1:
The ECC functionality is segmented into two distinct parts: local ECC circuits distributed in each MRAM macro for error detection, and a shared global ECC circuit for error correction. This segmentation allows each macro to have minimal local circuitry (only detection logic) while sharing the complex correction logic globally, thus reducing per-macro area overhead while maintaining detection capability.
Solution Approach 2:
The global ECC circuit serves as a universal resource shared by multiple MRAM macros. Instead of each macro having a complete ECC circuit, the global circuit performs correction functions for all macros that require correction, making the system more area-efficient while maintaining full error correction capability across all memory macros.
2Reliability
If both local and shared ECC circuitry are implemented, then error correction effectiveness is improved, but power consumption increases
Solution Approach 1:
The ECC system is divided into local detection circuits (low power) and global correction circuits (higher power but shared). By segmenting the functionality, most memory operations only activate the low-power local detection circuits, while the higher-power global correction circuits are only activated when errors are detected, thus reducing average power consumption while maintaining correction effectiveness.
Solution Approach 2:
The error correction process operates periodically rather than continuously: local detection circuits continuously monitor for errors, but the global correction circuit is only activated when an error is detected. This periodic activation of the power-intensive correction logic significantly reduces average power consumption while maintaining the ability to correct errors when they occur.
3Reliability
If error data is transmitted globally for correction, then error correction capability is improved, but latency and energy consumption increase
Solution Approach 1:
Error detection is performed preliminarily by local ECC circuits before global correction is needed. This preliminary detection action allows the system to identify errors locally and prepare for correction, enabling the global correction circuit to process only actual errors rather than all data, thus reducing the latency and data transmission requirements for global correction operations.
Data Source
AI summary
A memory device, such as a MRAM device, includes a plurality of memory macros, where each includes an array of memory cells and a first ECC circuit configured to detect data errors in the respective memory macro. A second ECC circuit that is remote from the plurality of memory macros is communicatively coupled to each of the plurality of memory macros. The second ECC circuit is configured to receive the detected data errors from the first ECC circuits of the plurality of memory macros and correct the data errors.