Hierarchical ECC for MRAM Error Correction With Lower Area Overhead
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Solution Overview
Problem
Existing memory devices, such as MRAM, face challenges in efficiently detecting and correcting errors caused by environmental and internal factors, leading to data corruption and system failures, which current error correction codes struggle to address effectively in terms of area requirements and power consumption.
Innovation Solution
A hierarchical ECC (Error Correction Code) structure is implemented, where local ECC circuits in each memory macro perform error detection, and a shared global ECC circuit handles error correction, balancing area requirements and power consumption by reducing the need for extensive ECC circuitry and data communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional ECC circuits are implemented in each memory macro, then error detection and correction capability is improved, but area overhead and power consumption increase significantly
Solution Approach 1:
The patent segments the ECC functionality into two distinct parts: local ECC circuits within each memory macro for error detection, and a shared global ECC circuit for error correction. This segmentation allows each component to be optimized independently, reducing the total area required while maintaining full error correction capability.
Solution Approach 2:
The global ECC circuit serves multiple memory macros simultaneously, making it a universal resource. Instead of dedicating separate ECC circuits to each memory macro, the shared global circuit handles correction for all macros, significantly reducing redundant circuitry and area overhead.
2Reliability
If traditional ECC circuits are implemented in each memory macro, then error detection and correction capability is improved, but power consumption increases
Solution Approach 1:
By segmenting ECC functions into local detection and global correction, the patent reduces the computational burden in each local circuit. The local ECC circuits only perform lightweight detection operations, while the global circuit handles the more power-intensive correction operations shared across multiple macros.
Solution Approach 2:
The shared global ECC circuit consolidates power consumption by serving multiple memory macros through a single correction engine. This eliminates the need for each macro to maintain its own full ECC correction capability, reducing overall power consumption while maintaining reliability.
3Reliability
If extensive ECC circuitry is implemented, then error correction reliability is improved, but device complexity increases
Solution Approach 1:
The patent simplifies device complexity by dividing ECC operations into two distinct stages: detection at the local level and correction at the global level. This segmentation creates clearer functional boundaries and simplifies the design of each individual circuit component.
Solution Approach 2:
The shared global ECC circuit provides a universal correction mechanism that simplifies the overall system architecture. Instead of each memory macro requiring independent full-featured ECC circuits, the universal global circuit handles correction for all macros, reducing redundancy and simplifying device complexity.
Data Source
AI summary
A memory device, such as a MRAM device, includes a plurality of memory macros, where each includes an array of memory cells and a first ECC circuit configured to detect data errors in the respective memory macro. A second ECC circuit that is remote from the plurality of memory macros is communicatively coupled to each of the plurality of memory macros. The second ECC circuit is configured to receive the detected data errors from the first ECC circuits of the plurality of memory macros and correct the data errors.