Multi-Layer MRAM Integration Density vs Wiring Delay
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Solution Overview
Problem
Integrated circuit devices with resistance variable memory elements face challenges in optimizing operation efficiency, particularly in multi-layer configurations, where power consumption and data processing speed are affected by wiring delays and current distribution across layers.
Innovation Solution
The configuration involves placing MTJ elements of different write times and currents in specific multi-layer positions, with faster MTJ elements closer to the semiconductor substrate and slower ones farther away, optimizing wiring lengths and current distribution to enhance operation efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If resistance variable memory elements are disposed in a multi-layer state to increase integration, then high integration is achieved, but wiring delay increases and operation efficiency decreases
Solution Approach 1:
The patent applies local quality by assigning different write currents to MTJ elements based on their specific layer position. First MTJ elements (closer to substrate) receive a first write current, while second MTJ elements (farther from substrate) receive a second write current. This localized differentiation compensates for wiring delay variations across layers, maintaining operation efficiency while achieving high integration through multi-layer configuration.
2Speed
If write current is increased to improve write speed, then operation speed improves, but power consumption increases
Solution Approach 1:
The patent changes the current parameter differentially across layers rather than using a uniform write current. By setting the first write current for first MTJ elements and a different second write current for second MTJ elements, the system optimizes write speed for each layer's specific wiring characteristics while minimizing overall power consumption. This parameter differentiation allows high-speed operation without excessive power consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the overall operation efficiency of integrated circuit devices by balancing power consumption and speed, reducing wiring delays, and allowing for high-speed operation while minimizing power usage.
Implementation Method 1
a magnetic random access memory (MRAM) including a magnetic tunnel junction element in which a tunnel magnetoresistance effect is used
Data Source
AI summary
An integrated circuit device of the invention, includes: a first resistance variable memory element provided on a semiconductor substrate; a second resistance variable memory element provided on the semiconductor substrate; and a semiconductor circuit for controlling write and read of the first resistance variable memory element and the second resistance variable memory element, which is provided on the semiconductor substrate, in which the second resistance variable memory element has a write current that is smaller than a write current of the first resistance variable memory element, and the second resistance variable memory element is disposed farther from the semiconductor substrate than the first resistance variable memory element.