MRAM Interconnect Capping for Etch Protection
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Solution Overview
Problem
The integration of magnetic random access memory (MRAM) devices onto interconnects with small dimensions and tight pitch sizes poses challenges due to alignment and etching issues, which affect the underlying materials and the device itself, hindering the commercialization of non-volatile embedded memory.
Innovation Solution
A conductive capping layer is formed over the conductive fill layer and diffusion barrier layer, providing etch protection and flexibility in etchant choice, with specific shapes and thicknesses to protect the interconnect during memory element patterning, allowing for precise integration of MRAM devices onto interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If MRAM devices are integrated onto interconnects with small dimensions and tight pitch sizes, then memory density and capacity are improved, but alignment precision and etching quality deteriorate due to the small feature sizes
Solution Approach 1:
A capping layer is formed over the interconnect structure before the memory device patterning step. This preliminary action protects the interconnect from etching damage and provides a defined surface for subsequent alignment, allowing precise placement of memory devices without directly exposing the vulnerable interconnect features to the patterning process
Solution Approach 2:
The capping layer serves as an intermediary between the interconnect and the memory device patterning process. It absorbs the harsh etching conditions and provides a sacrificial layer that protects the underlying interconnect, enabling precise memory device formation without compromising interconnect integrity
2Ease of manufacture
If standard etching processes are used for MRAM device patterning, then manufacturing simplicity is maintained, but the interconnect materials suffer from sputtering and corrosion damage
Solution Approach 1:
The capping layer is deposited beforehand to cushion and absorb the harmful effects of the etching process. This protective layer prevents direct exposure of the interconnect materials to sputtering and corrosion, allowing the use of standard etching processes without damaging the interconnect
Solution Approach 2:
The capping layer is designed to be consumed or modified during the etching process, converting the potentially harmful etching conditions into a beneficial protective mechanism. The layer that would otherwise be waste material serves as a sacrificial shield, transforming the etching process from a harmful direct exposure into a controlled protective mechanism
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the successful integration of MRAM devices onto interconnects, addressing alignment and etching challenges, and enhances the performance and reliability of non-volatile memory by protecting the copper interconnects from unwanted sputtering and corrosion.
Implementation Method 1
A conductive capping layer is formed over the conductive fill layer and diffusion barrier layer, providing etch protection and flexibility in etchant choice
Implementation Method 2
protecting the copper interconnects from unwanted sputtering and corrosion
Data Source
AI summary
Approaches for an interconnect cladding process for integrating magnetic random access memory (MRAM) devices, and the resulting structures, are described. In an example, a memory structure includes an interconnect disposed in a trench of a dielectric layer above a substrate, the interconnect including a diffusion barrier layer disposed at a bottom of and along sidewalls of the trench to an uppermost surface of the dielectric layer, a conductive fill layer disposed on the diffusion barrier layer and recessed below the uppermost surface of the dielectric layer and an uppermost surface of the diffusion barrier layer, and a conductive capping layer disposed on the conductive fill layer and between sidewall portions of the diffusion barrier layer. A memory element is disposed on the conductive capping layer of the interconnect.