MRAM Interconnect Formation Using Etch Stop Layers
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Solution Overview
Problem
The formation of electrical connections in magnetic tunnel junction memory cells within integrated circuits is prone to errors due to process variations in chemical mechanical planarization and etching, leading to either permanent opens or shorts, resulting in a low percentage of functional MRAM cells.
Innovation Solution
The use of a memory cell etch stop layer and a capping layer to facilitate accurate connection of the MRAM cell to an overlying interconnect, involving the formation of a capping layer over the memory cell, a covering layer, and a memory cell etch stop, with the interconnect being in electrical communication with the memory cell, ensuring precise exposure and connection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If CMP and etching processes are used to form interconnects to the top layer, then the interconnects can be formed through the dielectric layer, but the process variation causes the interconnects to be either too short (permanent open) or too long (permanent short)
Solution Approach 1:
A capping layer is formed over the top layer before the CMP and etching processes. This capping layer serves as a preliminary protective structure that defines the exact termination point of the etching process, ensuring the interconnects reach the precise depth needed to contact the top layer without penetrating through it and causing shorts.
Solution Approach 2:
The capping layer acts as an intermediary layer between the top layer and the overlying dielectric layer. It provides a distinct etch stop that mediates the etching process, allowing precise control of etch depth to reach the top layer surface without compromising the top layer integrity.
2Volume of moving object
If the top layer is made thin (40 nm or less) to reduce MRAM cell size, then the cell size is reduced, but the process variation in CMP and etching becomes more significant relative to the layer thickness
Solution Approach 1:
The capping layer is formed in advance over the thin top layer, providing a robust reference plane for subsequent processing. This preliminary structure compensates for the thinness of the top layer, ensuring that even with process variations, the interconnects will accurately reach the top layer surface without causing opens or shorts.
Solution Approach 2:
The capping layer provides a cushion or buffer zone above the thin top layer. This beforehand cushioning protects the top layer from over-etching or damage during the interconnect formation process, absorbing process variations that would otherwise be critical given the thin top layer dimensions.
3Reliability
If the interconnect is formed to reach the top layer surface, then electrical connection is achieved, but the interconnect may pass through the top layer causing a short
Solution Approach 1:
The capping layer serves as an intermediary that defines the precise termination point for the etching process. It allows the interconnect to reach the top layer surface for reliable electrical connection while preventing the etch from penetrating through the top layer, thereby eliminating the short circuit risk.
Solution Approach 2:
The capping layer is formed beforehand to establish a controlled etch stop. This preliminary structure ensures that the interconnect formation process terminates exactly at the desired depth, achieving reliable electrical contact without creating harmful shorts through the top layer.
Data Source
AI summary
Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, a method for producing an integrated circuit includes forming a memory cell with a memory cell upper surface. A capping layer is formed overlying the memory cell, and a portion of the capping layer is removed to expose the memory cell upper surface. A memory cell etch stop is formed overlying the memory cell upper surface after the portion of the capping layer is removed to expose the memory cell upper surface. The memory cell etch stop is removed from overlying the memory cell upper surface, and an interconnect is formed in electrical communication with the memory cell.