MRAM Cell Metal Interconnects for Sub-7nm Pitch Scaling
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Solution Overview
Problem
The downscaling of semiconductor memory devices, particularly in vertical magnetoresistive random-access memory (MRAM) structures, faces challenges in forming low resistance interconnects due to difficulties in creating copper-filled lined cavities, and conventional damascene processes yield very tall metal interconnects that are not co-planar with MRAM cell structures, requiring structural accommodations for element pitch scaling less than 7 nanometers.
Innovation Solution
A method of fabricating MRAM devices involving the formation of a stack with hard masks, sidewall spacers, and interconnect metal lines, where a third hard mask is used to create co-planar surfaces, followed by patterning and etching to form fully aligned vias and fill them with conductive material, allowing for the reduction of interconnect height and adaptation to smaller pitches without the need for additional space or steps in the damascene process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional damascene processes are used to form interconnects, then low resistance interconnects can be formed, but the metal interconnects become very tall and are not co-planar with MRAM cell structures
Solution Approach 1:
The patent transitions from planar interconnect formation to three-dimensional conformal coating, depositing the interconnect metal around and above the MRAM cell structures. This dimensional change allows the interconnects to wrap around the vertical MRAM stacks, achieving both low resistance through adequate metal cross-section and proper height alignment through the conformal deposition process
Solution Approach 2:
The interconnect metal is deposited around and above the MRAM cell structures, with the metal nesting around the vertical stacks. The sidewall spacers are then formed around the MRAM stacks, and the interconnect metal is recessed to be coplanar with the top of the sidewall spacers, creating a nested structure that achieves coplanarity while maintaining low resistance
2Area of moving object
If device elements are downscaled to pitches less than 7 nanometers, then memory density increases, but the ability to use damascene processes with low resistance interconnects diminishes
Solution Approach 1:
The patent uses three-dimensional conformal deposition to form interconnects that wrap around vertical MRAM stacks, enabling scaling to pitches less than 7 nanometers. This approach maintains adequate interconnect cross-sectional area for low resistance while achieving the required small footprints for high density
Solution Approach 2:
The interconnect formation process is segmented into multiple steps: initial metal deposition around stacks, sidewall spacer formation, metal recessing, and via formation. This segmentation allows each step to be optimized independently, making the overall process manageable at sub-7nm pitches
Data Source
AI summary
A method of fabricating an MRAM device, the method including forming a magnetoresistive random-access memory (MRAM) stack comprising a first hard mask, forming sidewall spacers adjacent to the MRAM stack, forming a layer of interconnect metal around and above the MRAM stack, recessing the interconnect metal, forming a layer of a second hard mask over the interconnect metal, and patterning and etching the second hard mask and interconnect metal, forming interconnect metal lines.