MRAM I/O Segmentation for DRAM-Level Speed
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Solution Overview
Problem
Conventional MRAMs have slower writing and reading speeds due to prolonged column-to-column delay time (tCCD) compared to DRAMs, and they cannot perform reading and writing operations simultaneously or read/write multiple memory cells concurrently.
Innovation Solution
The MRAM design includes multiple I/O units with selection circuits and voltage controllers that allow simultaneous reading and writing of different data into multiple memory cells, reducing tCCD by enabling concurrent operations across multiple memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional MRAM writing operation is used with single I/O unit, then writing operation can be completed, but writing speed is slower than DRAM due to prolonged column-to-column delay time
Solution Approach 1:
The patent divides the I/O unit into multiple independent I/O units (IO0-IO7), each capable of independent reading and writing operations. This segmentation allows parallel operations across multiple memory cells, reducing the column-to-column delay time and improving writing speed to match or exceed DRAM performance.
Solution Approach 2:
The patent introduces a new dimension of parallelism by enabling each I/O unit to simultaneously perform reading and writing operations on different memory cells. This dual-operation capability across multiple I/O units creates a multi-dimensional parallel processing architecture that dramatically reduces delay time.
2Speed
If conventional MRAM reading operation is used with single I/O unit, then reading operation can be completed, but reading speed is slower than DRAM due to prolonged column-to-column delay time
Solution Approach 1:
The patent segments the reading function across multiple independent I/O units, each with its own sensing amplifier. This allows simultaneous reading operations on multiple memory cells, reducing the column-to-column delay time and improving reading speed to match or exceed DRAM performance.
Solution Approach 2:
The patent enables each I/O unit to simultaneously perform reading and writing operations, adding a temporal dimension of parallelism. This allows reading operations to occur concurrently with writing operations across different memory cells, dramatically reducing overall access time.
3Productivity
If conventional MRAM uses single I/O unit, then device complexity is low, but simultaneous reading and writing operations on multiple memory cells cannot be performed
Solution Approach 1:
The patent divides the memory system into multiple independent I/O units, each with dedicated bit lines, source lines, and sensing amplifiers. This segmentation enables concurrent reading and writing operations on different memory cells, dramatically improving productivity while the modular design keeps individual unit complexity manageable.
Solution Approach 2:
Each I/O unit is designed with universal functionality to perform both reading and writing operations simultaneously on different memory cells. This multi-functionality is achieved through shared voltage controllers and flexible selection circuits, improving productivity without proportionally increasing overall device complexity.
4Productivity
If conventional MRAM uses shared voltage controllers for reading and writing, then device complexity is reduced, but reading and writing operations cannot be performed simultaneously
Solution Approach 1:
The patent segments the voltage control function by providing separate voltage controllers (first voltage controller for writing, second voltage controller for reading) that operate independently. This allows simultaneous reading and writing operations without interference, improving productivity while maintaining manageable device complexity through functional separation.
Solution Approach 2:
The patent introduces selection circuits as intermediaries that manage the connection between memory cells and I/O units based on operation type. These selection circuits coordinate the independent voltage controllers, enabling simultaneous read/write operations while maintaining clear signal paths and preventing interference between operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves read/write tCCD equal to or shorter than DRAMs, allowing for faster data rates and simultaneous operations on multiple memory cells, thereby enhancing the overall performance of MRAMs.
Implementation Method 1
a magnetoresistive memory cell MC, which stores one bit of data
Implementation Method 2
a sensing amplifier 18, which is used to read data from the memory cell MC
Data Source
AI summary
A magnetoresistive random access memory (MRAM) includes a plurality of input/output units. Each input/output units can read and write memory cells simultaneously. So a read/write column to column delay time (tCCD) of the MRAM is equal to or shorter than a read/write column to column delay time of a dynamic random access memory (DRAM). Consequently, a data-rate of the MRAM is equal to or shorter than a data-rate of the DRAM.