MRAM Array Local Source Line Reduction
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Solution Overview
Problem
The scalability of spin-torque magnetoresistive random access memory (MRAM) is limited by the number of metal connect lines, particularly source lines and bitlines, which require significant area in standard CMOS processes and are not easily accessible to circuitry outside the memory array.
Innovation Solution
A simplified fabrication process and structure for MRAM arrays are introduced, where local source lines are connected only to specific memory elements within the array, reducing the need for external circuitry access and allowing current to be applied through a subset of bitlines to change the state of memory elements, thereby eliminating the requirement for a lower source line.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional source lines and bitlines are used in ST-MRAM, then memory elements can be accessed and programmed, but the number of metal connect lines increases, limiting scalability and requiring significant area in standard CMOS processes
Solution Approach 1:
The patent extracts and eliminates the need for separate source lines by repurposing existing bitlines to serve dual functions. The bitline is used both for reading memory elements and for writing data through spin-torque switching, removing the harmful complexity of additional metal connect lines and improving scalability.
Solution Approach 2:
The bitline is designed to perform multiple functions: it serves as a read path for sensing memory element states and as a write path for programming memory elements through spin-torque switching. This multi-functionality reduces the total number of metal connect lines required, directly addressing the scalability limitation.
2Ease of operation
If separate source lines are provided for each row group, then memory elements can be selectively accessed, but the area required for source lines and their connections increases significantly
Solution Approach 1:
The patent merges the source line function into the bitline structure. Instead of providing separate source lines for each row group, the bitline is extended to serve as both the word line and source line, eliminating the need for additional connection areas and reducing overall cell area while maintaining selective access capability.
Solution Approach 2:
The patent transitions from a two-dimensional layout requiring separate source and bit lines to a three-dimensional stacked architecture where memory elements are arranged vertically above the bitline. This dimensional change allows selective access without requiring additional planar area for source lines, significantly reducing the area required for connections.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the complexity and area requirements for MRAM arrays, enhancing scalability and fabrication efficiency by minimizing the number of source lines and bitlines accessible to external circuitry, while maintaining the non-volatility and high-speed operation of MRAM technology.
Implementation Method 1
The angular momentum carried by the spinpolarized tunneling current causes reversal of the free layer
Implementation Method 2
exhibits an electrical resistance that depends on the magnetic state of the device
Data Source
AI summary
A memory is provided that simplifies a fabrication process and structure by reducing the number of source lines and bitlines accessible to circuitry outside of the memory array. The memory has first and second row groups comprising a plurality of memory elements each coupled to one each of a plurality of M bit lines; first and second local source lines and first and second word lines, each coupled to each of the plurality of memory elements; and circuitry coupled to the first and second word lines and configured to select one of the first and second row groups, and coupled to the plurality of M bit lines and configured to apply current of magnitude N through the memory element in the selected row group coupled to one of the plurality of M bit lines by applying current of magnitude less than N to two or more of the remaining M-1 bit lines.