MRAM Logic Integration via Dual Damascene Interconnects
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Solution Overview
Problem
Current methods for integrating magnetic random access memory (MRAM) cells with logic devices in integrated circuits face challenges in compatibility and cost-effectiveness, making it difficult to form MRAM cells that are compatible with logic processing and integrate them into a single chip efficiently.
Innovation Solution
A method and device structure that involve forming a substrate with distinct regions for memory and logic components, using a dual damascene interconnect process to couple MRAM cells with metal lines, and employing a dielectric layer with multiple interconnect levels to facilitate the integration of MRAM cells with logic transistors on the same substrate, allowing for simultaneous formation of memory and logic components using logic processing techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If MRAM cells are integrated with logic devices using conventional methods, then memory and logic components can be formed on the same chip, but the manufacturing process becomes complex and costly requiring additional masks and tools
Solution Approach 1:
The patent applies universality by using the logic device interconnect structure to serve dual purposes: connecting logic components and connecting MRAM cells. The same metal lines and vias that interconnect logic transistors are also used to connect to MRAM cell electrodes, eliminating the need for separate interconnect structures for memory devices. This multi-functional approach reduces manufacturing complexity while maintaining full integration capability.
2Reliability
If separate processes are used for MRAM and logic device fabrication, then each component can be optimized independently, but the overall manufacturing cost increases and production time extends
Solution Approach 1:
The patent merges the fabrication processes for logic devices and MRAM cells into a unified sequence. Both component types are formed on the same substrate using the same deposition, etching, and patterning tools. The interconnect structures are formed simultaneously for both logic and memory regions, eliminating the need for separate fabrication lines and reducing overall production time while maintaining component quality.
3Reliability
If additional dedicated interconnect structures are created for MRAM cells, then reliable electrical connection is achieved, but the device complexity and manufacturing cost increase
Solution Approach 1:
The patent makes the logic device interconnect structures universal by designing them to serve both logic and memory functions. The metal lines and vias are routed and dimensioned to provide reliable electrical connections to both logic transistor terminals and MRAM cell electrodes. This eliminates the need for dedicated MRAM interconnect structures while maintaining connection reliability through proper design of the shared interconnect network.
Data Source
AI summary
Integrating magnetic random access memory with logic is disclosed. The magnetic tunnel junction stack of a magnetic memory cell is disposed within a dielectric layer which serves as a via level of an interlevel dielectric layer with a metal level above the via level. An integration scheme for forming dual damascene structures for interconnects can be formed to logic and memory cells easily.