MRAM Logic Integration via Segmented Interconnects
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Solution Overview
Problem
Magnetic random access memory (MRAM) devices face challenges in alignment and integration with logic devices due to non-transparent metal layers, leading to inoperability and the need for complex, costly manufacturing processes with multiple masks.
Innovation Solution
A method for forming MRAM cells with magnetic tunnel junction (MTJ) elements on a substrate, using a dual damascene interconnect in one region and a damascene interconnect in another, with a bottom electrode directly contacting a metal line, allowing for simplified integration with logic components and reduced mask usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If MTJ stack layers are patterned using lithography and etch techniques, then the memory structure is formed, but the non-transparent metal layers prevent proper alignment with underlying interconnect structures
Solution Approach 1:
The patent segments the interconnect structure into multiple levels: lower interconnect structures formed first, then MTJ stack layers, then upper interconnect structures. This segmentation allows each layer to be formed and aligned independently, with the upper interconnect level providing the necessary alignment reference for lithography patterning of subsequent layers.
Solution Approach 2:
The patent performs preliminary formation of the lower interconnect structures and MTJ stack layers before forming the upper interconnect structures. This preliminary action establishes a foundation that guides subsequent alignment and patterning operations, ensuring proper registration of metal lines with underlying structures.
2Adaptability or versatility
If multiple masks are used for integrating MRAM components with logic devices, then complete integration is achieved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent creates a universal interconnect architecture where the upper interconnect level serves multiple functions: it provides alignment references for lithography, connects MTJ stack layers to lower interconnect structures, and interfaces with logic device interconnects. This multi-functionality reduces the need for separate dedicated structures for each purpose.
Solution Approach 2:
The patent merges the alignment reference function with the interconnect function by making the upper interconnect level itself serve as the alignment reference. This eliminates the need for separate alignment marks or additional mask steps, combining multiple functions into a single structural element.
3Adaptability or versatility
If MRAM cells are integrated with logic gates and electronic components, then functionality is enhanced, but manufacturing compatibility challenges arise
Solution Approach 1:
The patent applies different interconnect formation approaches to different regions: dual damascene interconnects in logic device regions and simplified damascene or direct contact in MRAM cell regions. This local differentiation allows each region to be optimized for its specific requirements while maintaining overall process compatibility.
Solution Approach 2:
The patent resolves manufacturing compatibility issues by transitioning to a three-dimensional stacked architecture where MRAM cells and logic devices occupy different vertical levels. This dimensional separation allows independent optimization of each device type while sharing the same substrate and manufacturing platform.
Data Source
AI summary
Device and methods of forming a device are disclosed. The method includes providing a substrate and a first upper dielectric layer over first, second and third regions of the substrate. The first upper dielectric layer includes a first upper interconnect level with a plurality of metal lines in the first and second regions. A MRAM cell which includes a MTJ element sandwiched between top and bottom electrodes is formed in the second region. The bottom electrode is in direct contact with the metal line in the first upper interconnect level of the second region. A dielectric layer which includes a second upper interconnect level with a dual damascene interconnect in the first region and a damascene interconnect in the second region is provided over the first upper dielectric layer. The dual damascene interconnect in the first region is coupled to the metal line in the first region and the damascene interconnect in the second region is coupled to the MTJ element.