MRAM Lower Electrode Contact Resistance Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing semiconductor memory devices, such as spin transfer magnetic random access memory (MRAM), face challenges with high contact resistance between lower electrodes and diffusion layers due to mismatched dimensions and alignment variations, which also increase chip costs and reduce heat resistance when silicide is formed.
Innovation Solution
The solution involves forming lower electrodes to match the dimensions and shape of the diffusion layers, increasing the contact area between the electrodes and diffusion layers, thereby reducing contact resistance and enhancing alignment precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicide is formed to reduce contact resistance, then contact resistance decreases, but chip costs increase and heat resistance decreases
Solution Approach 1:
The patent extracts and eliminates the silicide formation process from the manufacturing flow by achieving low contact resistance through dimensional matching and increased contact area between the lower electrode and diffusion layer, thereby removing the source of high cost and heat resistance issues while maintaining the desired electrical performance
2Reliability
If lower electrode dimensions are reduced to match diffusion layer dimensions, then contact area increases and contact resistance decreases, but manufacturing precision requirements increase
Solution Approach 1:
The patent merges the dimensioning of the lower electrode with the diffusion layer dimensions, making them substantially identical in size and shape. This dimensional matching ensures that the lower electrode automatically aligns with the diffusion layer, maximizing contact area while simplifying the manufacturing process and reducing alignment precision requirements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces contact resistance and maintains chip performance while minimizing costs and heat resistance issues associated with silicide formation.
Implementation Method 1
The magnetoresistive element is configured to store data in accordance with a magnetization state change
Implementation Method 2
The storage layer has perpendicular magnetic anisotropy
Implementation Method 3
a spin injection layer configured to inject spins into the storage layer in accordance with a current flow direction
Implementation Method 4
The MTJ element stores binary 1 or 0 depending on whether the magnetization states of the two magnetic layers, that is, the directions of spins in the two magnetic layers, are parallel or anti-parallel to each other
Implementation Method 5
The MTJ element comprises two magnetic layers (ferromagnetic layers) and a nonmagnetic layer formed between the magnetic layers
Data Source
AI summary
According to one embodiment, a semiconductor memory device comprises a cell transistor includes a first gate electrode buried in a semiconductor substrate and a first diffusion layer and a second diffusion layer formed to sandwich the first gate electrode, a first lower electrode formed on the first diffusion layer, a magnetoresistive element formed on the first lower electrode to store data according to a change in a magnetization state and connected to a bit line located above, a second lower electrode formed on the second diffusion layer, and a first contact formed on the second lower electrode and connected to a source line located above. A contact area between the second lower electrode and the second diffusion layer is larger than a contact area between the first contact and the second lower electrode.