MRAM Memory Control Circuit with Local Buffer and Sense Amplifier
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Solution Overview
Problem
Current memory control systems face challenges in achieving both high capacity and fast operation speed, with prefetching techniques like row buffers being ineffective for new addresses and causing overhead when predictions fail, and MRAMs being slow in reading time due to their mechanism of retaining data using minute resistance changes.
Innovation Solution
A memory control circuit is designed with a local buffer of smaller capacity than the cache memory, using MRAM cells and a capacitor connected in series with a magnetoresistive element, where the cache controller generates new addresses for prefetching by incrementing or decrementing the requested address, and a sense amplifier senses data logic from the voltage variation due to current through the magnetoresistive element, allowing for rapid data access and reduced latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If prefetching is used to transfer data in advance, then data waiting time is shortened, but large overhead is caused when prediction fails
Solution Approach 1:
The patent applies preliminary action by implementing a row buffer that stores recently accessed data in advance, enabling fast retrieval when the same address is accessed again. The controller proactively manages the row buffer by replacing entries based on access patterns, preparing data before it is needed to reduce latency without excessive overhead.
2Speed
If row buffer is used to store recently accessed data, then high-speed data access is realized for repeated addresses, but not effective for accessing new addresses
Solution Approach 1:
The patent applies dynamics by implementing a dynamic row buffer replacement strategy where the controller actively manages buffer entries based on access patterns. The system adapts its behavior by replacing buffer entries when access patterns indicate a need for new data, allowing it to maintain high speed for repeated addresses while adapting to new address access requirements.
3Stability of the object's composition
If MRAM cells are used to retain data using resistance changes, then non-volatile storage is achieved, but reading time is slow
Solution Approach 1:
The patent applies segmentation by dividing the memory system into two parts: a small row buffer for fast access of recently used data, and a larger main memory array for bulk storage. This segmentation allows the system to achieve fast reading speeds for frequently accessed data while maintaining the non-volatile storage capabilities of MRAM for the overall memory capacity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution achieves a 10% to 30% speed-up in access times for newly generated addresses and improves processor instruction-execution efficiency by reducing latency and power consumption, while maintaining a high hit rate and memory access speed compared to conventional SRAMs.
Implementation Method 1
a capacitor connected in series to the magnetoresistive element; and a sense amplifier to sense a logic of the data from a voltage between both electrodes of the capacitor, the voltage varying in accordance with a current flowing through the magnetoresistive element
Implementation Method 2
each MRAM cell including of a magnetoresistive element to store data... a sense amplifier to sense a logic of the data from a voltage between both electrodes of the capacitor, the voltage varying in accordance with a current flowing through the magnetoresistive element
Data Source
AI summary
A memory control circuit to control a first memory comprising a plurality of MRAM cells, each MRAM cell including of a magnetoresistive element to store data, has a second memory, when there is a read request to a first address of the first memory, to read data of a second address different from the first address, from the first memory and store the read data, a controller to control access to the first memory and the second memory, a capacitor connected in series to the magnetoresistive element, and a sense amplifier to sense a logic of the data from a voltage between both electrodes of the capacitor, the voltage varying in accordance with a current flowing through the magnetoresistive element.