MRAM MTJ Stack with Decoupled Annealing for High TMR
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Solution Overview
Problem
Conventional MRAM devices face limitations in achieving a tunneling magnetoresistance ratio (TMR) of above 200% at a resistance area product (RA) of 10 Ohms.µm² due to issues such as loss of perpendicular magnetic anisotropy and metal diffusion during high thermal budgets, which affect the quality of the magnetic layers.
Innovation Solution
A stack design for MRAM devices with specific in-plane textures for the substrate, electrode, and seed metal layers, combined with a decoupled thermal budget annealing process, including a high-temperature anneal after forming the tunnel barrier layer and a lower-temperature anneal after forming the reference layer, to enhance the crystallinity and quality of the tunnel barrier layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a high thermal budget of 400°C and more is used during fabrication to improve crystallinity and interface quality, then the TMR can be increased, but the perpendicular magnetic anisotropy is lost and metal diffusion occurs deteriorating layer properties
Solution Approach 1:
The patent segments the thermal processing into distinct stages: a first high-temperature annealing step (400-500°C) performed after depositing only the tunnel barrier layer to achieve crystallinity and (001) orientation, followed by a second lower-temperature annealing step (200-400°C) after completing the full MTJ stack. This segmentation allows the tunnel barrier to receive the high thermal budget needed for optimal crystallinity while the magnetic layers are protected from excessive heat that would cause PMA loss and metal diffusion.
Solution Approach 2:
The patent applies preliminary high-temperature annealing to the tunnel barrier layer before depositing the magnetic layers. By performing the first annealing step (400-500°C) after depositing only the MgO tunnel barrier and removing the sacrificial layer, the tunnel barrier achieves optimal crystallinity and (001) orientation in advance. Subsequent magnetic layers are then deposited on this pre-prepared crystalline substrate and subjected to milder thermal conditions, preventing PMA loss and metal diffusion.
2Ease of manufacture
If conventional MTJ structures are used, then fabrication is simpler, but the TMR remains limited to ≤200% at RA ≥ 10 Ohms.µm²
Solution Approach 1:
The patent changes critical parameters of the tunnel barrier layer: achieving (001) crystal orientation instead of random orientation, optimizing thickness to 2-4 nm, and controlling interface quality through selective annealing. These parameter changes enable TMR ≥ 200% at RA < 10 Ohms.µm². The decoupled thermal budget process specifically enables the (001) orientation by providing 400-500°C annealing to the tunnel barrier before magnetic layer deposition, which is not achievable in conventional single-stage processes.
Solution Approach 2:
The patent applies local quality optimization by treating the tunnel barrier layer differently from the magnetic layers. The tunnel barrier receives high-temperature annealing (400-500°C) to achieve optimal crystallinity and (001) orientation, while the magnetic layers are protected from such high temperatures to maintain their PMA. This localized differential treatment of thermal processing enables both high TMR and preserved magnetic properties.
3Manufacturing precision
If the reference layer is arranged on top of the stack (top-pinned approach), then some improvement in TMR is achieved, but challenges with back end of line processing exist due to high annealing temperatures
Solution Approach 1:
The patent segments the thermal processing timeline to resolve BEOL compatibility issues. The first high-temperature annealing (400-500°C) occurs early in the process after tunnel barrier deposition but before magnetic layer completion. The second annealing (200-400°C) occurs after full stack assembly. This segmentation ensures that when BEOL processing occurs later, the stack has already achieved optimal tunnel barrier crystallinity and can withstand subsequent processing temperatures without losing PMA or experiencing excessive metal diffusion.
Solution Approach 2:
The patent performs preliminary high-temperature annealing of the tunnel barrier before completing the MTJ stack and before BEOL processing. By achieving optimal tunnel barrier crystallinity and (001) orientation in advance (first annealing step at 400-500°C), the stack is better prepared to withstand subsequent BEOL processing temperatures. The magnetic layers are then deposited on this pre-optimized tunnel barrier and protected from high temperatures that would cause PMA loss.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed stack achieves a TMR of 200% or more at RA < 10 Ohms.µm², improving the performance and reliability of MRAM devices by maintaining perpendicular magnetic anisotropy and reducing metal diffusion.
Implementation Method 1
the stored information can be read-out by determining a tunneling magnetoresistance between the free layer and the reference layer through the tunnel barrier layer
Implementation Method 2
An improved crystallinity of the MgO tunnel barrier layer, as well as an improved interface quality of the layers, could increase the TMR
Data Source
Figure 1
Figure 2
Figure 3(a)~3(b)
AI summary
The present disclosure presents a stack (10) for an MRAM device, wherein the stack (11) includes a magnetic tunnel junction (MTJ) with a high tunneling magnetoresistance ratio (TMR). The stack (11) comprises a substrate layer (11), a first electrode layer (12) arranged on the substrate layer (11), and a seed metal layer (13) arranged on the first electrode layer (12), each layer having a [001] or [010] or [100] in-plane texture. The stack (11) further comprises a magnetic free layer (14) arranged on the seed metal layer (13), a crystalline tunnel barrier layer (15) arranged on the free layer (14), a magnetic reference layer (16) arranged on the crystalline tunnel barrier layer (15), a pinning layer (17) arranged on the reference layer (16), and a second electrode layer (18) arranged on the pinning layer (17).