MRAM MTJ Stack Etching for Electrical Isolation

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Solution Overview

Problem

Existing semiconductor memory technologies face challenges in preventing unwanted electrical connections between magnetic layers in magnetoresistive random access memory (MRAM) devices due to metal residues generated during the manufacturing process, which can affect the reliability and performance of the memory cells.

Innovation Solution

The formation of a magnetic tunnel junction (MTJ) stack within a semiconductor structure, where the MTJ stack is carefully etched to prevent metal residues from creating electrical connections between the first and second magnetic layers, using a combination of etching processes and spacer layers to control the etching and positioning of the tunnel barrier and magnetic layers, ensuring the magnetic moments of the ferromagnetic free and pinned layers can be accurately aligned to represent digital signals without unwanted electrical paths.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If metal residues are generated during the manufacturing process, then the etching process is simplified, but unwanted electrical connections between magnetic layers occur

Engineering Contradiction:
Improveetching process simplicityVSAvoidelectrical connection reliability
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

A dielectric layer is introduced as an intermediary between the first and second magnetic layers. This dielectric layer prevents unwanted electrical connections between the magnetic layers while allowing the etching process to proceed. The dielectric material acts as a mediator that blocks electrical pathways without interfering with the magnetic functionality of the device.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Manufacturing precision

If the tunnel barrier layer is made thinner to improve electron tunneling, then the resistance state changes more effectively, but unwanted electrical connections through metal residues increase

Engineering Contradiction:
Improvemagnetic moment alignment precisionVSAvoidelectrical isolation reliability
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The dielectric layer serves as a mediator that enables the use of thinner tunnel barrier layers without compromising electrical isolation. By providing an additional isolation layer, the system can achieve better magnetic moment alignment through thinner barriers while the dielectric prevents short circuits through any remaining metal residues.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Area of stationary object

If the magnetic layers are positioned closer together to reduce device size, then the memory cell area is reduced, but unwanted electrical connections between layers increase

Engineering Contradiction:
Improvememory cell areaVSAvoidlayer isolation reliability
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The dielectric layer enables closer positioning of magnetic layers by providing electrical isolation. This intermediary layer allows the system to reduce the vertical distance between magnetic layers for smaller memory cell area while maintaining reliable electrical isolation against unwanted connections.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively prevents unwanted electrical connections between the magnetic layers, enhancing the reliability and performance of MRAM devices by ensuring precise control over the magnetic alignment and resistance states, thereby improving the digital signal representation and memory cell functionality.

Implementation Method 1

The tunnel barrier layer is thin enough (such a few nanometers) to permit electrons to tunnel from one ferromagnetic layer to the other

Methodology Applied
Scientific EffectQuantum tunneling:

Implementation Method 2

A resistance of the MTJ stack is adjusted by changing a direction of a magnetic moment of the ferromagnetic free layer with respect to that of the ferromagnetic pinned layer

Methodology Applied
Scientific EffectMagnetoresistance: Magnetoresistance

Data Source

PatentUS11171284B2Memory device
Publication Date: 2021.11.09 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11171284B2 patent drawing
  • US11171284B2 patent drawing
  • US11171284B2 patent drawing

AI summary

A memory device includes a bottom electrode, an MTJ stack, and a top electrode. The bottom electrode has a lower sidewall and an upper sidewall above the lower sidewall and laterally set back from the lower sidewall. The MTJ stack is over the bottom electrode. The MTJ stack includes a bottom magnetic layer, a tunnel barrier layer over the bottom magnetic layer and a top magnetic layer over the tunnel barrier layer. The bottom magnetic layer has a sidewall coterminous with the upper sidewall of the bottom electrode. The top magnetic layer has a sidewall laterally set back from the upper sidewall of the bottom electrode. The top electrode is over the MTJ stack.