MRAM MTJ Pillar Structure for Void-Free Interlayer Dielectric
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Solution Overview
Problem
Conventional magnetoresistive random-access memory (MRAM) devices face challenges in forming void-free interlayer dielectric material between adjacent MTJ pillars, leading to shorts and yield loss due to increasing aspect ratios and decreasing pitch between MRAM devices.
Innovation Solution
A semiconductor structure with tapered sidewalls and void-free interlayer dielectric material is formed by sequentially depositing and patterning each layer of the MTJ pillar, using different dielectric materials for encapsulation and depositing ILD in gaps with low aspect ratios to prevent void formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional MRAM devices are formed with single-layer interlayer dielectric between adjacent MTJ pillars, then manufacturing process is simple, but voids form in the ILD leading to shorts and yield loss
Solution Approach 1:
The interlayer dielectric is divided into multiple sequential layers (first ILD layer, second ILD layer, third ILD layer) deposited at different stages. Each layer is deposited when the MTJ pillar structure is at a different height, ensuring that each ILD layer fills gaps with low aspect ratio and prevents void formation between adjacent pillars
Solution Approach 2:
The first ILD layer is deposited preliminarily over the bottom electrode before subsequent MTJ layers are formed. This preliminary deposition establishes a foundation that prevents voids from forming in later ILD layers, as each subsequent layer builds upon the previously deposited structure
2Productivity
If pitch between adjacent MRAM devices is decreased to increase device density, then productivity increases, but aspect ratio of ILD gaps increases leading to void formation
Solution Approach 1:
By segmenting the ILD deposition into multiple layers deposited at different MTJ pillar heights, the effective gap depth for each deposition step is reduced. This allows pitch to be decreased for higher density while maintaining low aspect ratio for each ILD layer, preventing void formation even in densely packed devices
Solution Approach 2:
The solution moves from a single-layer ILD approach (one-dimensional filling) to a multi-layer sequential deposition approach (adding temporal and structural dimensions). Each ILD layer is deposited when MTJ pillars are at different heights, effectively reducing the aspect ratio in the vertical dimension while maintaining high horizontal density
3Reliability
If multiple layers of interlayer dielectric are deposited to prevent voids, then ILD void-free quality improves, but manufacturing process complexity increases
Solution Approach 1:
Each ILD layer is deposited preliminarily at a specific stage of MTJ pillar construction, before subsequent layers are added. This preliminary timing ensures that each ILD layer fills gaps with minimal aspect ratio, making the manufacturing process systematic and predictable despite multiple layers
Solution Approach 2:
The deposition parameters (timing, thickness, material composition) of each ILD layer are optimized based on the current MTJ pillar height and structure. By changing parameters dynamically across the three deposition stages, the process achieves void-free filling while maintaining manufacturing feasibility
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures void-free ILD layers between MTJ pillars, reducing shorts and improving MRAM device yield by maintaining a low aspect ratio for ILD gap fill, even in densely packed devices.
Implementation Method 1
forming two adjacent top electrodes on the two adjacent portions of the free layer using an angled ion beam etch process
Implementation Method 2
depositing a reference layer on two adjacent bottom electrodes and the first layer of ILD material
Implementation Method 3
depositing a tunnel barrier layer over the remaining portions of the reference layer
Data Source
AI summary
A semiconductor structure with a magnetic tunnel junction (MTJ) pillar for a magnetoresistive random-access memory (MRAM) device, where each material layer of the MTJ pillar resides on a lower material layer of the MTJ pillar with a different width. Embodiments of the present invention provide a top electrode with a tapered shape. Embodiments of the present invention also provide a dielectric encapsulation layer around the reference layer and around the free layer. The dielectric encapsulation material surrounding a sidewall of the reference layer is composed of a different dielectric encapsulation material than the dielectric encapsulation around the sidewall of the free layer.