Negative Word Line Biasing for MRAM Read Margin Improvement
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Solution Overview
Problem
MOSFET transistors in MRAM arrays experience significant sub-threshold leakage currents that increase exponentially with temperature, degrading read margins in high-temperature environments, and existing body bias techniques are inefficient in large memories and bulk CMOS technology.
Innovation Solution
An electronic biasing circuit and method that applies a negative DC bias voltage to the gates of unselected MOSFET transistors in a memory array to minimize leakage current, using a DC bias current source to generate a negative DC bias voltage signal delivered to the read/word lines of unselected rows during a read operation, effectively reducing leakage current and enhancing read margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If body bias (VBB) is applied to raise the threshold voltage of transistors to control sub-threshold leakage current, then leakage current reduction is achieved, but the negative voltage levels must be pumped to larger levels, increasing area and supply current
Solution Approach 1:
The patent applies a negative voltage to the gate of the pass transistor instead of using body bias. This changes the parameter being controlled from body voltage to gate voltage, achieving leakage current reduction without requiring high-voltage pumping circuits, thereby reducing the area and supply current requirements
2Object-generated harmful factors
If body bias (VBB) is applied to raise the threshold voltage, then leakage current is reduced, but the negative voltage must be pumped to larger levels, increasing supply current
Solution Approach 1:
By switching from body bias to gate bias with negative voltage, the patent achieves leakage control without requiring high-voltage pumping, thereby reducing the supply current consumption of the bias voltage generators
3Object-generated harmful factors
If threshold voltage is shifted to reduce leakage current, then sub-threshold leakage is controlled, but the resistances of switches in their on state are affected
Solution Approach 1:
The patent applies negative voltage specifically to the gate of the pass transistor only when needed for leakage control during read operations. This localized and conditional application allows leakage reduction without permanently altering the threshold voltage, thereby maintaining normal on-state resistance characteristics when the negative bias is not applied
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The negative DC bias voltage effectively reduces leakage current through unselected memory cells, thereby improving the read margin of selected memory cells in high-temperature environments, maintaining accurate data reading by minimizing current stealing from selected rows.
Implementation Method 1
MOSFET transistors share the characteristic of having a sub-threshold (leakage) current present due to finite sub-threshold slope resulting in some (not zero) unwanted current
Data Source
AI summary
An electronic biasing circuit for memory operating in a high temperature environment, comprising a first memory cell and a second memory cell, a first MOSFET transistor electrically coupled in series with the first memory cell, wherein the first MOSFET transistor is configured as a switch, a second MOSFET transistor electrically coupled in series with the second memory cell, wherein the second MOSFET transistor is configured as a switch, a DC bias current source configured to generate a negative DC bias voltage signal, a first read/word line electrically coupled to a gate of the first MOSFET transistor, and a second read/word line electrically coupled to a gate of the second MOSFET transistor, wherein in response to a read operation of the first memory cell, the second read/word line is configured to deliver the negative DC bias voltage signal to the gate of the second MOSFET transistor.